Patents Assigned to Advanced Micro Devices
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Publication number: 20110055308Abstract: Systems and methods for multi-precision computation are disclosed. One embodiment of the present invention includes a plurality of multiply-add units (MADDs) configured to perform one or more single precision operations and an arrangement generator to generate one or more mantissa arrangements using a plurality of double precision numbers. Each MADD is configured to receive and load said mantissa arrangements from the arrangement generator. The MADDs compute a result of a multi-precision computation using the mantissa arrangements. In an embodiment, the MADDs are configured to simultaneously perform operations that include, single precision operations, double-precision additions and double-precision multiply and additions.Type: ApplicationFiled: June 10, 2010Publication date: March 3, 2011Applicant: Advanced Micro Devices, Inc.Inventors: Michael J. Mantor, Jeffrey T. Brady, Daniel B. Clifton, Christopher Spencer
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Publication number: 20110055511Abstract: A method of allocating a memory to a plurality of concurrent threads is presented. The method includes dynamically determining writer threads each having at least one pending write to the memory; and dynamically allocating respective contiguous blocks in the memory for each of the writer threads. Another method of allocating a memory to a plurality of concurrent threads includes launching the plurality of threads as a plurality of wavefronts, dynamically determining a group of wavefronts each having at least one thread requiring a write to the memory, and dynamically allocating respective contiguous blocks in the memory for each wavefront from the group of wavefronts.Type: ApplicationFiled: September 3, 2009Publication date: March 3, 2011Applicant: Advanced Micro Devices, Inc.Inventors: Michael MANTOR, John MCCARDLE, Marcos ZINI, Brian EMBERLING
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Publication number: 20110050710Abstract: Disclosed herein is a graphics-processing unit (GPU) having an internal memory for general-purpose use and applications thereof. Such a GPU includes a first internal memory, an execution unit coupled to the first internal memory, and an interface configured to couple the first internal memory to a second internal memory of an other processing unit. The first internal memory may comprise a stacked dynamic random access memory (DRAM) or an embedded DRAM. The interface may be further configured to couple the first internal memory to a display device. The GPU may also include another interface configured to couple the first internal memory to a central processing unit. In addition, the GPU may be embodied in software and/or included in a computing system.Type: ApplicationFiled: November 11, 2009Publication date: March 3, 2011Applicant: Advanced Micro Devices, Inc.Inventors: Greg SADOWSKI, Konstantine Iourcha, John Brothers
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Publication number: 20110050713Abstract: An apparatus and methods for scheduling and executing commands issued by a first processor, such as a CPU, on a second processor, such as a GPU, are disclosed. In one embodiment, a method of executing processes on a graphics processing unit (GPU) includes monitoring one or more buffers in a memory, selecting a first subset from the one or more buffers for execution on the GPU based on a workload profile of the GPU, and executing the first subset on the GPU. The GPU may also receive a priority ordering of the one or more buffers, where the selecting is further based on the received priority ordering. By performing prioritization and scheduling of commands in the GPU, system performance is enhanced.Type: ApplicationFiled: September 3, 2009Publication date: March 3, 2011Applicant: Advanced Micro Devices, Inc.Inventors: Rex McCrary, Frank Liljeros, Gongxian Jefferey Cheng
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Publication number: 20110050716Abstract: A processor includes a first shader engine and a second shader engine. The first shader engine is configured to process pixel shaders for a first subset of pixels to be displayed on a display device. The second shader engine is configured to process pixel shaders for a second subset of pixels to be displayed on the display device. Both the first and second shader engines are also configured to process general-compute shaders and non-pixel graphics shaders. The processor may also include a level-one (L1) data cache, coupled to and positioned between the first and second shader engines.Type: ApplicationFiled: January 21, 2010Publication date: March 3, 2011Applicant: Advanced Micro Devices, Inc.Inventors: Michael MANTOR, Ralph C. Taylor, Jeffrey T. Brady
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Patent number: 7899570Abstract: The present disclosure relates to automatic deposition profile targeting with a combined deposition/polishing apparatus which obtains matching deposition and subsequent polishing profiles by use of feedback data from an advanced polish endpoint system in an advanced process control system.Type: GrantFiled: February 27, 2008Date of Patent: March 1, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Thomas Ortleb, Markus Nopper, Thomas Roessler
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Patent number: 7897433Abstract: Various semiconductor chip reinforcement structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip that has a side and forming a polymer layer on the side. The polymer layer has a central portion and a first frame portion spatially separated from the central portion to define a first channel. An underfill material may be provided to invade the channel and establish a mechanical joint between the polymer layer and the underfill material.Type: GrantFiled: February 18, 2009Date of Patent: March 1, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Michael Su, Frank Kuechenmeister, Jaime Bravo
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Patent number: 7899634Abstract: A method, apparatus, and a system for generating a binary mapping of wafer regions using measured value. A first measured value relating to processing a first workpiece is acquired. A second measured value relating to a second workpiece is acquired. At least a first region common to the first and second workpieces is defined. A determination is made as to whether the results associated with the first or second measured value is above a predetermined threshold. A first binary value is assigned to the first region based upon a determination that the results associated the first or second measured value data is above the threshold.Type: GrantFiled: November 7, 2005Date of Patent: March 1, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Michael G. McIntyre, Michael A. Retersdorf
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Patent number: 7893503Abstract: By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer of the base semiconductor material, well-established process techniques for forming the gate dielectric may be used. In some illustrative embodiments, a substantially self-aligned process is provided in which the gate electrode may be formed on the basis of layer, which has also been used for defining the central portion of the base semiconductor material of one of the active regions. Hence, by using a single semiconductor alloy, the performance of transistors of different conductivity types may be individually enhanced.Type: GrantFiled: April 6, 2010Date of Patent: February 22, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Sven Beyer, Manfred Horstmann, Patrick Press, Wolfgang Buchholtz
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Patent number: 7893493Abstract: An intermediate hybrid surface orientation structure may include a silicon-on-insulator (SOI) substrate adhered to a bulk silicon substrate, the silicon of the SOI substrate having a different surface orientation than that of the bulk silicon substrate, and a reachthrough region extending through the SOI substrate to the bulk silicon substrate, the reachthrough region including a silicon nitride liner over a silicon oxide liner and a silicon epitaxially grown from the bulk silicon substrate, the epitaxially grown silicon extending into an undercut into the silicon oxide liner under the silicon nitride liner, wherein the epitaxially grown silicon is substantially stacking fault free.Type: GrantFiled: July 10, 2006Date of Patent: February 22, 2011Assignees: International Business Machines Corproation, Advanced Micro Devices, Inc.Inventors: Yun-Yu Wang, Linda Black, Judson R. Holt, Woo-Hyeong Lee, Scott Luning, Christopher D. Sheraw
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Patent number: 7893496Abstract: Stress enhanced MOS transistors are provided. A semiconductor device is provided that comprises a semiconductor-on-insulator structure, a gate insulator layer, a source region, a drain region and a conductive gate overlying the gate insulator layer. The semiconductor-on-insulator structure comprises: a substrate, a semiconductor layer, and an insulating layer disposed between the substrate and the semiconductor layer. The semiconductor layer has a first surface, a second surface and a first region.Type: GrantFiled: December 22, 2009Date of Patent: February 22, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Igor Peidous, Rohit Pal
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Patent number: 7890078Abstract: A dual band WLAN (Wireless Local Area Network) communications technique is provided where a frequency synthesizer unit generates an LO (Local Oscillator) signal at a frequency between both frequency bands and two downconversion units and/or two upconversion units are provided. One of the units performs conversion between the LO signal and an IF (Intermediate Frequency) signal while the other conversion takes place between the IF signal and a zero-IF or low-IF signal. Signal processing is performed on the zero-IF or low-IF signal.Type: GrantFiled: January 25, 2010Date of Patent: February 15, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Wolfram Kluge, Sascha Beyer, Jeannette Zarbock
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Patent number: 7890702Abstract: A computer system and method. In one embodiment, a computer system comprises a processor and a cache memory. The processor executes a prefetch instruction to prefetch a block of data words into the cache memory. In one embodiment, the cache memory comprises a plurality of cache levels. The processor selects one of the cache levels based on a value of a prefetch instruction parameter indicating the temporal locality of data to be prefetched. In a further embodiment, individual words are prefetched from non-contiguous memory addresses. A single execution of the prefetch instruction allows the processor to prefetch multiple blocks into the cache memory. The number of data words in each block, the number of blocks, an address interval between each data word of each block, and an address interval between each block to be prefetched are indicated by parameters of the prefetch instruction.Type: GrantFiled: November 26, 2007Date of Patent: February 15, 2011Assignee: Advanced Micro Devices, Inc.Inventor: Gary Lauterbach
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Patent number: 7890138Abstract: A portable computer system such as a laptop computer system includes a computing subsystem that includes a processor that may execute instructions that implement application software, and a storage coupled to the processor that may store information. The laptop computer system also includes a wireless subsystem that may communicate with a wireless network. In addition, the wireless subsystem may receive an incoming communication and determine whether a requesting user is an authorized user. The processor may retrieve at least a portion of the information from the storage and send the retrieved information to a destination via email, for example, in response to a request by the requesting user for the information.Type: GrantFiled: June 30, 2006Date of Patent: February 15, 2011Assignee: Advanced Micro Devices, Inc.Inventors: R. Stephen Polzin, William T. Edwards
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Patent number: 7889512Abstract: A technique for observing signaling on the traces between ICs on a PC board without introducing significant signal degradation is provided. A route-through connector footprint allows the use of a standard connector without the use of stub traces. The route-through connector footprint allows a standard connector to be introduced directly into the line traces routed between ICs. Because stub traces are not used, this technique for mechanical interconnection into the line traces on a PC board allows for a single board layout to be used for both test and production. Additionally, because stub traces are not used, signal quality is minimally impacted and testing can be performed at operational speeds improving the reliability of the test function. The use of a route-through connector footprint additionally saves PC board space and cost.Type: GrantFiled: October 11, 2002Date of Patent: February 15, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Michael J. Borsch, Steven R. Klassen, Sanjiv Lakhanpal
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Patent number: 7884030Abstract: During semiconductor fabrication homogeneous gap-filling is achieved by depositing a thin dielectric layer into the gap, post deposition curing, and then repeating deposition and post deposition curing until gap-filling is completed. Embodiments include depositing a layer of low deposition temperature gap-fill dielectric into a high aspect ratio opening, such as a shallow trench or a gap between closely spaced apart gate electrode structures, as at a thickness of about 10 ? to about 500 ?, curing after deposition, as by UV radiation or by heating at a temperature of about 400° C. to about 1000° C., depositing another layer of low deposition temperature gap-filled dielectric, and curing after deposition. Embodiments include separately depositing and separately curing multiple layers.Type: GrantFiled: April 21, 2006Date of Patent: February 8, 2011Assignee: Advanced Micro Devices, Inc. and Spansion LLCInventors: Alexander Nickel, Lu You, Hirokazu Tokuno, Minh Tran, Minh Van Ngo, Hieu Pham, Erik Wilson, Robert Huertas
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Patent number: 7885627Abstract: An OFDM wireless transceiver uses a digital automatic gain control (AGC) module. The digital AGC module is configured for setting a gain to an initial gain value for mapping a received wireless signal to a first power value for an input circuit having a prescribed input range. The initial gain value is set relative to the prescribed input range and a prescribed signal to noise ratio. If the digital AGC module determines that the first power value of the received wireless signal does not exceed the prescribed input range, the digital AGC module calculates an optimum gain for the received wireless signal relative to the initial gain value and the first power value; if the first power value exceeds the prescribed input range, the AGC module determines the optimum gain based on setting the gain to a minimum gain value.Type: GrantFiled: July 7, 2003Date of Patent: February 8, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Christine Lee, Chien-Meen Hwang, Yong Li
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Patent number: 7884633Abstract: Various apparatus and methods of testing a semiconductor chip for soft defects are disclosed. In one aspect, a method of testing a semiconductor chip that has a surface and plural circuit structures positioned beneath the surface is provided. An external stimulus is applied to a series of fractional portions of the surface to perturb portions of the plural circuit structures such that at least one of the series of fractional portions is smaller than another of the series of fractional portions. The semiconductor chip is caused to perform a test pattern during the application of external stimulus to each of the fractional portions to determine if a soft defect exists in any of the series of fractional portions.Type: GrantFiled: June 4, 2008Date of Patent: February 8, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Ronald M. Potok, Rama R. Goruganthu, David E. Kloster, Norman E. Rhodes
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Patent number: 7885222Abstract: A method for scheduling tasks for execution by a mobile device is provided. A connectivity prerequisite is defined for a task scheduled to be executed by the mobile device. Connectivity state information associated with the mobile device is received. The connectivity prerequisite is compared to the connectivity state information. The task is executed responsive to the connectivity state information satisfying the connectivity prerequisite.Type: GrantFiled: September 29, 2006Date of Patent: February 8, 2011Assignee: Advanced Micro Devices, Inc.Inventor: Terry L. Cole
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Patent number: 7884650Abstract: A digital compensation of an input stage of a comparator may be achieved by providing switched load elements, which may be appropriately connected to the differential input pair of the comparator in order to match transistor characteristics of the input pair and also match the load value of the input stage. Thus, enhanced offset behavior may be accomplished without providing an external signal and/or without requiring complex reference voltages/currents.Type: GrantFiled: November 14, 2008Date of Patent: February 8, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Sreenivasa Chalamala, Matthias Baer
