Abstract: Provided is a method for synchronizing a multiple carrier receiver to receive a transmitted signal. The method includes determining a location of one or more scattered pilot carriers in a received symbol sequence and modulating the scattered pilot carriers in accordance with a single pseudorandom binary sequence. The method also includes performing phase error correction via the modulated scattered pilot carriers.

Abstract: A portable computer system such as a laptop computer, for example, includes a first processor that may execute instructions corresponding to application software during a first mode of operation. The portable computer system also includes a second processor that may execute the instructions during a second mode of operation. The first processor and the second processor may be heterogeneous processors. Further, operation of the first processor and the second processor in the first mode and the second mode may be dependent upon which of a plurality of system preferences have been selected.

Abstract: By embedding a silicon/germanium mixture in a silicon layer of high tensile strain, a moderately high degree of tensile strain may be maintained in the silicon/germanium mixture, thereby enabling increased performance of N-channel transistors on the basis of silicon/germanium material. In other regions, the germanium concentration may be varied to provide different levels of tensile or compressive strain.

Abstract: A method and an apparatus for routing a semiconductor wafer to at least one of a plurality of processing tools based upon tool performance. Data relating to a performance of a first processing tool and a performance of a second processing tool is acquired. A semiconductor wafer is routed to one of the first processing tool or the second processing tool based upon a comparison between the performance of the first processing tool and the performance of the second processing tool using a controller.

Abstract: A system for protecting data during high-speed bidirectional communication between a master device and a slave device. The master device may control data transfer between the master device and the slave device. In addition, the master device may perform a read request to the slave device for a first data block associated with a first address and a second data block associated with a second address. In response, the slave device may send to the master device a portion of the first data block in a first burst and a portion of the second data block in a second burst via a plurality of bidirectional data paths. The slave device may further generate and send to the master device via one or more unidirectional data paths a cyclic redundancy code (CRC) based upon the first data block and the second data block.

Abstract: An AC coupled receiver incorporates a decision feedback restore technique that is readily implemented on a monolithic integrated circuit to reduce or eliminate effects of baseline wander in a non-return-to-zero (NRZ) data receiver. In at least one embodiment of the invention, a method includes at least substantially attenuating at least a DC portion of a received signal to generate a first signal. The method includes generating a low frequency signal based at least in part on a reference signal selected from a plurality of reference signals. The method includes generating a restored signal based at least in part on the first signal and the low frequency signal.

Abstract: A low contact resistance CMOS integrated circuit and method for its fabrication are provided. The CMOS integrated circuit comprises a first transition metal electrically coupled to the N-type circuit regions and a second transition metal different than the first transition metal electrically coupled to the P-type circuit regions. A conductive barrier layer overlies each of the first transition metal and the second transition metal and a plug metal overlies the conductive barrier layer.

Abstract: By performing x-ray analysis of stacked metallization layers on the basis of data reduction, the crystalline structure of individual metallization layers may be determined. Consequently, a relationship between electromigration and crystallinity, as well as a correlation between process parameters and materials and the finally obtained crystalline structures of metal lines, may be estimated in a highly efficient manner compared to measurement techniques based on charged particles.

Abstract: A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using the available processing resources to produce resulting data, and the resulting data is passed to an input/output device.

Abstract: A method includes collecting trace data associated with a plurality of device testers. Tester health metrics are generated for each of the device testers. The tester health metrics are analyzed to identify a selected tester health metric that diverges from the plurality of tester health metrics. A corrective action is initiated for the tester associated with the selected tester health metric. A method includes collecting trace data associated with a plurality of device testers. The trace data for each of the device testers is compared to a reference trace data set to generate tester health metrics for each of the device testers based on the difference therebetween. The tester health metrics are analyzed to identify a selected tester health metric that diverges from the plurality of tester health metrics. A corrective action is initiated for the tester associated with the selected tester health metric.

Abstract: The present invention provides a method and apparatus for scheduling a plurality of processing tools. The method comprises providing a first processing tool and a plurality of second processing tools, selecting one of the plurality of second processing tools, and determining a target output parameter of a combination of processing tools comprising said first processing tool and said selected one of the plurality of second processing tools. The method also includes determining at least one input parameter of a process model for controlling the first processing tool based upon the target output parameter of the combination of processing tools.

Abstract: A method for providing an integrated circuit with an option of increasing performance after fabrication is disclosed. The method includes performing a performance increase operation which increases the performance of the integrated circuit from a first performance level to a second performance level after the integrated circuit is fabricated.

Abstract: A circuit for de-emphasizing information transmitted via a differential communication link includes a voltage mode differential circuit and a bi-directional current source circuit. The voltage mode differential circuit includes a first and second output terminal. The voltage mode differential circuit provides a first voltage via the first output terminal and second voltage via the second output terminal in response to a differential input voltage. The bi-directional current source circuit is operatively coupled between the first and second terminals. The bi-directional current source circuit selectively provides current in a first and second direction between the first and second terminals based on the first and second voltage.

Abstract: By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.

Abstract: An apparatus and method obtains cipher block chaining mode (CBC) ciphertext blocks that were encrypted using a cipher block chaining encryption method, such a audio or video, and decrypts the CBC ciphertext blocks that were encrypted using the cipher block chaining encryption method using a multistage counter mode (CTR) decryptor to produce blocks of plaintext data from the CBC ciphertext blocks. In one example, cipher block chaining mode (CBC) information is translated (e.g., rearranged) to random counter mode (CTR) information so that a multistage counter mode (CTR) decryptor decrypts CBC ciphertext blocks into corresponding decrypted CBC plaintext blocks, in a parallel fashion, based on the translated CBC information. As such, apparatus with CTR hardware can be used to decrypt CBC or CFB ciphertext blocks.

Abstract: A system and method are provided to facilitate dual damascene interconnect integration in a single imprint step. The method provides for creation of a translucent imprint mold with three-dimensional features comprising the dual damascene pattern to be imprinted. The imprint mold is brought into contact with a photopolymerizable organosilicon imaging layer deposited upon a transfer layer which is spin coated or otherwise deposited upon a dielectric layer of a substrate. When the photopolymerizable layer is exposed to a source of illumination, it cures with a structure matching the dual damascene pattern of the imprint mold. A halogen breakthrough etch followed by oxygen transfer etch transfer the vias from the imaging layer into the transfer layer. A second halogen breakthrough etch followed by a second oxygen transfer etch transfer the trenches from the imaging layer into the transfer layer. A dielectric etch transfers the pattern from the transfer layer into the dielectric layer.

Abstract: The method and accompanying apparatus provides secure register access. In one example, as part of a secure boot process, data is written into a managed secure register (MSR) register and access policy data is written into programmable MSR policy registers. During run-time, the MSR register securely stores data in compliance with the programmable register access policy data. Access policy is enforced during run-time based on the programmable register access policy data.

Abstract: Miniaturized complex transistor devices are formed with reduced leakage and reduced miller capacitance. Embodiments include transistors having reduced capacitance between the gate electrode and source/drain contact, as by utilizing a low-K dielectric constant sidewall spacer material. An embodiment includes forming a gate electrode on a semiconductor substrate, forming a sidewall spacer on the side surfaces of the gate electrode, forming source/drain regions by ion implantation, forming an interlayer dielectric over the gate electrode, sidewall spacers, and substrate, and forming a source/drain contact through the interlayer dielectric. The sidewall spacers and interlayer dielectric are then removed. A dielectric material, such as a low-K dielectric material, is then deposited in the gap between the gate electrode and the source/drain contact so that an air gap is formed, thereby reducing the parasitic “miller” capacitance.

Abstract: The device and accompanying apparatus and method provides security among a calling function, such as an any executable code, and at least one target function, such as any executable code that the calling function wishes to have execute. In one example, the device includes an engine operative to perform run-time verification of the signatures of secure interrupt handler code and at least one target function before allowing execution of the at least one target function. If both the secure interrupt handler code's signature and the at least one target function's signature are successfully verified, the at least one target function is allowed to execute.

Abstract: The method and accompanying apparatus and device protects against programming attacks and/or data corruption by computer viruses, malicious code, or other types of corruption. In one example, signature verification policy information that identifies a plurality of policies associated with a plurality of target memory segments is programmed during a secure boot process. The programmed signature verification policy information associated with each of the plurality of target memory segments is then evaluated during run-time. Signature verification is then repeatedly performed, during run-time, on each of the plurality of target memory segments based on the programmed signature verification policy information associated with each target memory segment.