Abstract: A television set which learns to work with a remote control unit not specifically designed to operate that television set. The television set enters a learning mode in response to the user pressing a “Learn Remote” button or menu item, or in response to receiving an unknown remote control signal value, and gives the user a series of prompts for the user to press specified buttons on the remote control unit. As the user presses the buttons, the television set associates the received data values with the prompted button/functionality, to construct the remote code data set of the remote control unit. The television set may retrieve the remote code data set from an external source such as a website. After learning the remote code data set, the television set is able to be controlled by the remote control unit as though it were factory original.
Abstract: An electronic circuit. The electronic circuit includes a first circuit leg coupled to a first supply voltage node and a second supply voltage node. The first circuit leg includes a first reference current circuit configured to produce a first reference current and a second reference current circuit configured to produce a second reference current. The electronic circuit further includes a second circuit leg coupled in parallel with the first circuit leg. The second circuit leg includes a first transistor coupled to form a current mirror with the first reference current circuit and a second transistor coupled to form a current mirror with the second reference current circuit. The source terminals of each of the first and second transistors are coupled together to form a third supply voltage node.
Type:
Grant
Filed:
January 23, 2008
Date of Patent:
January 26, 2010
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Dimitry Patent, Ravinder Rachala, Shawn Searles, Lena Ahlen, Matthew Cooke
Abstract: An integrated circuit chip is provided that comprises on-chip memory and test circuitry. The test circuitry is configured to perform operational testing of the on-chip memory. The test circuitry comprises a controller which is configured to perform a selection out of a plurality of test algorithms to perform the operational testing. The plurality of test algorithms includes a fault detection test algorithm to perform operational testing of the on-chip memory in order to detect whether or not there is a memory fault, without locating the memory fault. The plurality of test algorithms further includes a fault location test algorithm to perform operational testing of the on-chip memory in order to detect and locate a memory fault. Further, a method to perform a memory built-in self test and an MBIST (Memory Built-In Self Test) control circuit template are provided.
Type:
Grant
Filed:
July 11, 2006
Date of Patent:
January 26, 2010
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Siegfried Kay Hesse, Markus Seuring, Thomas Herrmann
Abstract: Thermal interface materials and method of using the same in packaging are provided. In one aspect, a thermal interface material is provided that includes an indium preform that has a first surface and a second surface opposite to the first surface, an interior portion and a peripheral boundary. The indium preform has a channel extending from the peripheral boundary towards the interior portion. The channel enables flux to liberate during thermal cycling.
Type:
Grant
Filed:
June 7, 2006
Date of Patent:
January 26, 2010
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Seah Sun Too, Hsiang Wan Liau, Janet Kirkland, Tek Seng Tan, Maxat Touzelbaev, Raj N. Master
Abstract: Receiver architectures and related bias circuits for a data processor are provided. One embodiment of a receiver architecture includes three linear receiver stages coupled in series. The first stage receives a differential data strobe (DQS) input signal associated with a plurality of data (DQ) signals, and the first stage has a first programmable swing voltage associated therewith. The second stage has a programmable shift voltage associated therewith, and the third stage has a second programmable swing voltage associated therewith. The receiver architecture also includes a programming architecture coupled to the first stage, the second stage, and the third stage. The programming architecture is configured to set the first programmable swing voltage, the programmable shift voltage, and the second programmable swing voltage.
Type:
Grant
Filed:
April 10, 2008
Date of Patent:
January 26, 2010
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Shawn Searles, Grace Chuang, Christopher M. Kurker, Curtis M. Brody
Abstract: A dual band WLAN (Wireless Local Area Network) communications technique is provided where a frequency synthesizer unit generates an LO (Local Oscillator) signal at a frequency between both frequency bands and two downconversion units and/or two upconversion units are provided. One of the units performs conversion between the LO signal and an IF (Intermediate Frequency) signal while the other conversion takes place between the IF signal and a zero-IF or low-IF signal. Signal processing is performed on the zero-IF or low-IF signal.
Abstract: Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.
Type:
Application
Filed:
July 21, 2008
Publication date:
January 21, 2010
Applicant:
Advanced Micro Devices, Inc.
Inventors:
Rohit PAL, Frank Bin YANG, Michael J. HARGROVE
Abstract: The present invention generally relates to a multidimensional thermal management device for an integrated circuit chip, and more particularly, to thermal management devices with a synthetic jet ejector adapted to operate along a hollow fin and a fin with cross-flow heat exchanger tubes. A thermal management device 50, a new circuit assembly 100 equipped with the new thermal management device 50, and a new guide for a synthetic jet ejector 20 for adapting the synthetic jet ejector technology to the new thermal management device 50 and associated circuit assembly 100 are disclosed.
Abstract: A system includes a processing device, at least one data processing module, and a security control module. The security control module is operatively connected to both the processing device and the data processing module. The security control module is operative to control access to a protected register that is associated with the at least one data processing module. As such, the security control module operates as a firewall or filter to allow or deny access to a protected register. Security-unaware data processing module are therefore secured in the system at a central location while eliminating the need to use only security-aware data processing module. A method for securing data processing modules, including security-unaware data processing module, is also disclosed.
Type:
Application
Filed:
July 21, 2008
Publication date:
January 21, 2010
Applicants:
ATI Technologies ULC, Advanced Micro Devices, Inc.
Abstract: Methods for removing metal-comprising materials from semiconductor materials are provided. In accordance with an exemplary embodiment, a method comprises providing a metal-comprising material overlying a semiconductor material and exposing the metal-comprising material to an aqueous non-chlorine-comprising acid solution having a pH of about less 7.
Abstract: Semiconductor devices and methods for fabricating semiconductor devices are provided. One exemplary method comprises providing a silicon-comprising substrate having a first surface, etching a recess into the first surface, the recess having a side surface and a bottom surface, implanting carbon ions into the side surface and the bottom surface, and forming an impurity-doped, silicon-comprising region overlying the side surface and the bottom surface.
Type:
Application
Filed:
July 21, 2008
Publication date:
January 21, 2010
Applicant:
Advanced Micro Devices, Inc.
Inventors:
Frank Bin YANG, Michael J. HARGROVE, Rohit PAL
Abstract: A method of manufacturing a semiconductor device structure, such as a FinFET device structure, is provided. The method begins by providing a substrate comprising a bulk semiconductor material, a first conductive fin structure formed from the bulk semiconductor material, and a second conductive fin structure formed from the bulk semiconductor material. The first conductive fin structure and the second conductive fin structure are separated by a gap. Next, spacers are formed in the gap and adjacent to the first conductive fin structure and the second conductive fin structure. Thereafter, an etching step etches the bulk semiconductor material, using the spacers as an etch mask, to form an isolation trench in the bulk semiconductor material. A dielectric material is formed in the isolation trench, over the spacers, over the first conductive fin structure, and over the second conductive fin structure.
Abstract: A structure and method is utilized to detect cracks, fissures, fractures, or other dislocations in an IC die. A conductive line in a metal layer is provided about the periphery of the IC die. A break in the conductive line indicates that the IC die is cracked. A JTAG interface can be utilized to provide an indication of whether the die is cracked.
Abstract: A method of estimating a time variant Orthogonal Frequency Division Multiplexing (OFDM) while eliminating Inter-carrier Interference (ICI) is disclosed, where the time variant channel matrix is estimated at channel taps using a Basis Expansion Model (BEM). The BEM method decomposes the time variant channel into a group of basis functions in the frequency domain. Coefficients are estimated using a sub-space tracking algorithm that decreases the dimensions of the coefficient matrix allowing for simpler calculation of the estimated signal. The coefficients matrix is estimated using a conjugate gradient iterative method that may be stopped after 6-8 iterations to arrive at an acceptable estimation. Finally, the transmitted data is estimated, again using the conjugate gradient method iteratively, wherein the conjugate gradient method is stopped after a small number of iterations.
Abstract: A computer system has multiple performance states. The computer system periodically determines utilization information for the computer system and adjusts the performance state according to the utilization information. If a performance increase is required, the computer system always goes to the maximum performance state. If a performance decrease is required, the computer system steps the performance state down to a next lower performance state.
Type:
Grant
Filed:
July 3, 2007
Date of Patent:
January 12, 2010
Assignee:
Advanced Micro Devices, Inc.
Inventors:
David F. Tobias, Evandro Menezes, Richard Russell, Morrie Altmejd
Abstract: An apparatus and method is described that provide an efficient blind channel estimation approach for PSK and DPSK modulated multicarrier communication systems. With the requirement that the channel phase difference between any two adjacent carriers is smaller than one half of the minimum phase difference between two symbols of the PSK or DPSK constellation, a low-complexity deterministic approach to channel estimation is devised. This approach is highly effective, robust, and particularly useful for time varying channels with low AWGN noise.
Abstract: Focus monitoring for a photolithographic applications is provided by illuminating a photoresist layer with a light beam transmitted through a first binary mask to define a circuit pattern on an underlying substrate and then illuminating the photoresist layer with an unbalanced off-axis light beam transmitted through a second binary mask. The second mask contains a shifting feature configuration in one portion, while another portion blocks light transmission to the chip design area of the photoresist. After development of the photoresist layer, the pattern formed by illumination of the second mask can be compared with a predefined reference feature on the photoresist layer to determine whether a shift, if any, is within acceptable focus limits.
Abstract: A power management method and mechanism for dynamically determining which of a plurality of blocks of an electrical device may be powered on or off. A device is contemplated which includes one or more power manageable groups. A power management unit associated with the apparatus is configured to detect instructions which are scheduled for execution, identify particular power group(s) which may be required for execution of the instruction, and convey an indication which prevents the particular power group(s) from entering a powered off state, in response to detecting said instruction. If the power management unit does not detect an incoming or pending instructions, for a predetermined period of time, which requires a particular power group(s) for execution, the power management unit may convey an indication which causes or permits the corresponding power group(s) to enter a powered off state.
Abstract: A messaging scheme to synchronize processes within a distributed memory multiprocessing computer system having two or more processing nodes interconnected using an interconnect structure of dual-unidirectional links. Each unidirectional link forms a point-to-point interconnect to transfer packetized information between two processing nodes. A lock acquisition request from a lock requesting node is placed into service by an arbitrating node when no previous lock requests are pending for service. The arbitrating node transmits a broadcast message to all nodes in the system, which, in turn, respond with a corresponding probe response message to inform the arbitrating node of cessation of issuance of new requests by the node sending the probe response message. The arbitrating node informs the lock requesting node of the requesting node's lock ownership by transmitting a target done message thereto.
Type:
Grant
Filed:
August 4, 2000
Date of Patent:
December 29, 2009
Assignees:
Advanced Micro Devices, Inc., Alpha Processor, Inc.
Inventors:
Derrick R. Meyer, Jonathan M. Owen, Mark D. Hummel, James B. Keller
Abstract: In one embodiment, a first node comprises at least one memory request source and a node controller coupled to the memory request source. The node controller comprises a remote hit predictor configured to predict a second node to have a coherent copy of a block addressed by a memory request generated by the memory request source, and the node controller is configured to issued a speculative probe to the second node responsive to the prediction and to the memory request.