Abstract: Precise and repeatable alignment performance using asymmetric illumination is achieved by properly structuring, as by segmenting, an alignment mark on a reticle of a photolithographic exposure apparatus as a function of the type of asymmetric illumination, thereby improving resolution and repeatability of an alignment mark formed on a target substrate. Embodiments include double exposure techniques using dipole illumination with an angularly segmented alignment mark, e.g., at 45°, such that the first-order diffracted light is sent at 45° from the initial position of the dipole illumination.

Abstract: A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).

Abstract: A method includes receiving a metrology report including metrology data collected by a metrology tool, position data associated with the metrology data, and context data associated with the metrology tool. A first coordinate system employed by the metrology tool is determined based on the context data. The position data is transformed from the first coordinate system to a second coordinate system to generate transformed position data. The transformed position data is associated with the metrology data.

Abstract: The present invention provides a method and apparatus for adjusting tool processing speeds based on work-in-process levels. The method includes determining at least one work-in-process level associated with a first processing tool and modifying a processing speed associated with the first processing tool based on said at least one work-in-process level.

Abstract: An apparatus includes a central processing unit having an output to provide a status indicator, a graphics controller having an output coupleable to a display interface, a cache comprising a plurality of cache lines, and memory controller having an input to receive the status indicator. The memory controller is configured to disable allocation of cache lines of the cache for cache misses for data requests from the graphics controller in response to the status indicator indicating the central processing unit is in an active mode. The memory controller further is configured to enable allocation of cache lines of the cache for cache misses for data requests from the graphics controller in response to the status indicator indicating the central processing unit is in an idle mode.

Abstract: Cu interconnects are formed with composite capping layers for reduced electromigration, improved adhesion between Cu and the capping layer, and reduced charge loss in associated non-volatile transistors. Embodiments include depositing a first relatively thin silicon nitride layer having a relatively high concentration of Si—H bonds on the upper surface of a layer of Cu for improved adhesion and reduced electromigration, and depositing a second relatively thick silicon nitride layer having a relatively low concentration of Si—H bonds on the first silicon nitride layer for reduced charge loss.

Abstract: A stress enhanced MOS transistor and methods for its fabrication are provided. In one embodiment the method comprises forming a gate electrode overlying and defining a channel region in a monocrystalline semiconductor substrate. A trench having a side surface facing the channel region is etched into the monocrystalline semiconductor substrate adjacent the channel region. The trench is filled with a second monocrystalline semiconductor material having a first concentration of a substitutional atom and with a third monocrystalline semiconductor material having a second concentration of the substitutional atom. The second monocrystalline semiconductor material is epitaxially grown to have a wall thickness along the side surface sufficient to exert a greater stress on the channel region than the stress that would be exerted by a monocrystalline semiconductor material having the second concentration if the trench was filled by the third monocrystalline material alone.

Abstract: A method includes logically organizing rasterized image data into a first matrix of pixel tiles and individually rotating each pixel tile so as to generate a corresponding pixel tile of a second matrix representing an orthogonal representation of the first matrix. Each pixel tile represents a set of buffer lines of a frame buffer storing rasterized image data. The pixel tile is rotated by accessing and storing each buffer line of pixel data in a set of tile buffers such that the pixel data for each pixel in the same column position of an adjacent row is stored in a different tile buffer so that the set of tile buffers can be individually accessed to obtain pixel data for a set of pixels in the same column position in adjacent rows. This obtained pixel data is written to a second frame buffer as a row of pixel data for the corresponding pixel tile of the second matrix.

Abstract: A cache read request is received at a cache comprising a plurality of data arrays, each of the data arrays comprising a plurality of ways. Cache line data from each most recently used way of each of the plurality of data arrays is selected in response to the cache read request and selecting a first data of the received cache line data from the most recently used way of the cache. An execution of an instruction is stalled if data identified by the cache read request is not present in the cache line data from the most recently used way of the cache. A second data from a most recently used way of one of the plurality of data arrays other than the most recently used data array is selected as comprising data identified by the cache read request. The second data is provided for use during the execution of the instruction.

Abstract: An automatic power level control circuit provides output power control of a transmitter device as used in wireless LAN applications in that an output signal is detected and a corresponding control voltage of a DAC in the base band section is corresponding adjusted. Preferably, the measurement of the output power is carried out during a first transmit cycle and the DAC is adjusted after completion of the first transmit cycle and prior to the begin of a subsequent transmit cycle. Thus, a reliable output level control is obtained with a minimum number of radio frequency components, wherein the control loop shows an enhanced stability due to the time-discrete control operation.

Abstract: Methods and network interface systems are provided for transferring data between a host and a network using a shared memory, in which separate data transfer queues are employed for transfer of data of different priorities. For receive data, the network interface scrutinizes the data and provides a corresponding entry in a receive data transfer queue of a particular priority according to the data. For transmit data, the network interface transmits data corresponding to entries in lower priority queues when all higher priority data has been transmitted or when a certain number of higher priority data frames have been transferred while a lower priority frame is waiting to be sent.

Abstract: A method for converting data includes generating a first data vector of data measurements related to processing of at least one workpiece. Each element of the first data vector is associated with at least one of a plurality of positions on the workpiece. A cumulative distribution of the elements in the first data vector is generated. An outlier region of the data measurements is identified based on the cumulative distribution. A binary outlier data vector is generated from the first data vector by assigning a first binary value to the data elements in the first data vector in the outlier region and assigning a second binary value to the remaining data elements in the first data vector.

Abstract: A block transfer technique is provided for controlling a data transfer to and/or from a WLAN (Wireless Local Area Network) device connected to a data processing system. The data processing system comprises an operating system independent access controller and a platform specific data block transfer engine. The operating system independent access controller is configured to prepare the platform specific data block transfer engine to perform the data transfer to and/or from the WLAN device.

Abstract: SOI semiconductor components and methods for their fabrication are provided wherein the SOI semiconductor components include an MOS transistor in the supporting semiconductor substrate. In accordance with one embodiment the component comprises a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The component includes source and drain regions of first conductivity type and first doping concentration in the first semiconductor layer. A channel region of second conductivity type is defined between the source and drain regions. A gate insulator and gate electrode overlie the channel region. A drift region of first conductivity type is located between the channel region and the drain region, the drift region having a second doping concentration less than the first doping concentration of first conductivity determining dopant.

Abstract: A system for processing tester information including receiving data from a tester and forming a user defined field for storing descriptive information. A bitmap is created and compressed into a compressed image. The user defined field and the compressed image are then combined into a data structure.

Abstract: By consuming a surface portion of polysilicon material or silicon material after implantation and prior to activation of dopants, contaminants may be efficiently removed, thereby significantly enhancing the process uniformity during a subsequent silicidation process. Hence, the defect rate during the silicidation process, for instance “missing silicide” defects, may be significantly reduced, thereby also enhancing the reliability of static RAM cells.

Abstract: By forming a capping layer after a CMP process for planarizing the surface topography of an ILD layer, any surface irregularities may be efficiently sealed, thereby reducing the risk for forming conductive surface irregularities during the further processing. Consequently, yield loss effects caused by leakage paths or short circuits in the first metallization layer may be significantly reduced.

Abstract: A stack comprising a dielectric interface layer, a high-k gate dielectric layer, a group IIA/IIIB element layer is formed in that order on a semiconductor substrate. A metal aluminum nitride layer and, optionally, a semiconductor layer are formed on the stack. The stack is annealed at a raised temperature, e.g., at about 1,000° C. so that the materials in the stack are mixed to form a mixed high-k gate dielectric layer. The mixed high-k gate dielectric layer is doped with a group IIA/IIIB element and aluminum, and has a lower effective oxide thickness (EOT) than a conventional gate stack containing no aluminum. The inventive mixed high-k gate dielectric layer is amenable to EOT scaling due to the absence of a dielectric interface layer, which is caused by scavenging, i.e. consumption of any dielectric interface layer, by the IIA/IIB elements and aluminum.

Abstract: The invention relates to a network interface system for interfacing a host system with a network. The network interface system includes a bus interface system, a media access control system, a memory system, and a security system. The security system is adapted to selectively perform security processing on incoming and outgoing data. The security system comprises a key buffer and a pipeline. The pipeline performs an algorithm for encryption, decryption, or authentication according to the current key in the key buffer. The security system generates a signal after the last data block of a frame has been associated with a copy of the current key and, in response to the signal, advances the current key in the key buffer to the key for the next frame. The pipeline can thereby process data blocks from two different frames at one time, even where the data blocks use different keys.

Abstract: In devices in which display data is read from a memory for display, display underflow in a processing block is alleviated by controlling a clock frequency driving the processing block. Stages of the processing block send underflow detection signals to underflow prevention logic. The underflow prevention logic controls the frequencies of clock signals generated by a clock generator to alleviate the underflow condition.