Patents Assigned to Advanced Micro Devices
  • Patent number: 7564737
    Abstract: In one aspect, there is provided a method for controlling data output by a memory device. The method may include receiving a first clock signal having a first frequency. Moreover, a second and third clock signals may be produced from the first clock signal. The second and third clock signals may have second and third frequencies, respectively, that are about equal to the first frequency. The second and third frequencies may be out of phase relative to each other. A controller may output a first data in response to a rising edge of the second clock signal and output a second data in response to another rising edge of the third clock signal.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: July 21, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Joseph D. Macri
  • Patent number: 7560777
    Abstract: An electrostatic discharge (“ESD”) protection circuit having dynamically configurable series-connected diodes and a method for manufacturing the ESD protection circuit. A doped region of P-type conductivity and a doped region of N-type conductivity are formed in an SOI layer of P-type conductivity, wherein the doped regions are laterally spaced apart by a portion of the SOI layer. At least one gate structure is formed on the SOI region that is between the N-type and P-type doped regions. During normal operation, a portion of the SOI region that is adjacent to and between the P-type and N-type doped regions is biased so that it becomes a region of N-type conductivity, thereby forming two series-connected diodes. During an ESD event, the bias is changed so that the region between the P-type and N-type doped regions becomes a region of P-type conductivity, thereby forming a single P-N junction diode.
    Type: Grant
    Filed: November 8, 2005
    Date of Patent: July 14, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Akram A. Salman, Stephen G. Beebe
  • Patent number: 7561541
    Abstract: A WLAN (Wireless Local Area Network) communication device for performing communication in a WLAN network is provided that comprises a physical connection unit, a physical connection oscillator, and a control unit. The physical connection unit is for providing a physical connection of the WLAN communication device to a wireless communication medium. The physical connection oscillator is for providing a physical connection clock signal to the physical connection unit. The control unit is for controlling operation of the physical connection oscillator. The WLAN communication device is operable in a communication mode and in a deep sleep mode. The control unit is adapted to deactivate the physical connection oscillator when the deep sleep mode is entered. Embodiments may provide an extended reduction of the power consumption of the WLAN communication device.
    Type: Grant
    Filed: August 24, 2004
    Date of Patent: July 14, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Tilo Ferchland, Ralf Flemming, Christian Wiencke
  • Patent number: 7561465
    Abstract: One embodiment of the invention relates to a method for refreshing a nonvolatile memory array. In the method, a threshold voltage of a multi-bit memory cell is analyzed to determine if it has drifted outside of a number of allowable voltage windows, wherein each allowable voltage windows corresponds to a different multi-bit value. If the threshold voltage of the cell has drifted outside of the number of allowable voltage states, then the cell is recovered by adjusting at least one voltage boundary of at least one of the number of allowable voltage states.
    Type: Grant
    Filed: March 16, 2007
    Date of Patent: July 14, 2009
    Assignees: Advanced Micro Devices, Inc., Spansion LLC
    Inventors: Bryan William Hancock, Nicholas H. Tripsas, Richard C. Blish, II
  • Patent number: 7560381
    Abstract: In an enhanced technique for electroless metal deposition, the substrate is heated to or above the operating temperature for the specific plating solution, while the plating solution may be maintained at a non-critical low temperature to substantially prevent spontaneous self-decomposition within the plating tool. Hence, significant advantages with respect to process control and cost of ownership may be achieved.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: July 14, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Markus Nopper, Axel Preusse, Matthias Bonkass
  • Patent number: 7561625
    Abstract: A method and apparatus for crosstalk reduction. In one embodiment, an electronic system includes a transmitter and a receiver coupled by a plurality of differential signal paths. A first differential signal path is adjacent to a second differential signal path, which is adjacent to a third. Data transmitted on a first differential signal path is scrambled with a first scrambler function, while data transmitted on a third differential signal path is scrambled with a second scrambler function, which is an inverse of the first scrambler function. Data transmitted on a second differential signal path is scrambled with a third scrambler function, while data transmitted on a fourth differential signal path is scrambled with a fourth scrambler function that is an inverse of the third.
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: July 14, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Shawn Searles, Gerald R. Talbot
  • Patent number: 7557035
    Abstract: The invention provides a method of exposing low-k dielectric films to microwave radiation to cure the dielectric films. Microwave curing reduces the cure-time necessary to achieve the desired mechanical properties in the low-k films, thus decreasing the thermal exposure time for the NiSi transistor contacts. A lower thermal budget for interconnect fabrication is necessary to prevent damage to the NiSi transistor contacts and minimize thermal stressing of previously formed interconnect layers. Microwave-cured dielectric films also have higher mechanical strength and strong adhesion to overlying layers deposited during subsequent semiconductor device manufacturing steps.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: July 7, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: E. Todd Ryan, John A. Iacoponi
  • Patent number: 7556996
    Abstract: A method of forming a field effect transistor comprises providing a substrate comprising, at least on a surface thereof, a first semiconductor material. A recess is formed in the substrate. The recess is filled with a second semiconductor material. The second semiconductor material has a different lattice constant than the first semiconductor material. A gate electrode is formed over the recess filled with the second semiconductor material.
    Type: Grant
    Filed: April 18, 2007
    Date of Patent: July 7, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christoph Schwan, Joe Bloomquist, Kai Frohberg, Manfred Horstmann
  • Patent number: 7558687
    Abstract: The present invention provides a method and apparatus for dynamic adjustment of a sensor sampling rate. The method includes providing a data collection plan indicative of at least one first sampling rate for at least one sensor associated with at least one processing tool, receiving tool trace data from the at least one sensor via a network, and modifying, based on the tool trace data and a bandwidth associated with the network, the data collection plan to indicate at least one second sampling rate different from a corresponding at least one first sampling rate.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: July 7, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Christopher A. Bode
  • Publication number: 20090167405
    Abstract: A level shifting circuit includes a first stage and a second stage. The first stage and second stage are operatively coupled to a first and second power supply. The first stage translates a differential input voltage into an intermediate differential voltage. The second stage translates the intermediate differential voltage into a differential output voltage and provides feedback to the first stage in response to translating the intermediate differential voltage. The first stage reduces current flow between the first and second power supply through the second stage in response to the feedback.
    Type: Application
    Filed: December 19, 2008
    Publication date: July 2, 2009
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Samu Suryanarayana, Arvind Bomdica, Yikai Liang
  • Publication number: 20090168854
    Abstract: A circuit for de-emphasizing information transmitted via a differential communication link includes a voltage mode differential circuit and a bi-directional current source circuit. The voltage mode differential circuit includes a first and second output terminal. The voltage mode differential circuit provides a first voltage via the first output terminal and second voltage via the second output terminal in response to a differential input voltage. The bi-directional current source circuit is operatively coupled between the first and second terminals. The bi-directional current source circuit selectively provides current in a first and second direction between the first and second terminals based on the first and second voltage.
    Type: Application
    Filed: February 18, 2008
    Publication date: July 2, 2009
    Applicant: Advanced Micro Devices
    Inventors: Yikai Liang, Arvind Bomdica, Min Xu, Ming-Ju Ml. Lee
  • Publication number: 20090167032
    Abstract: A portable mobile device includes a first component and a second component movably connected to the first component. The first and second component are configured to be movable with respect to each other during the normal operation of the portable computing device. The portable computing device further includes a current generator connected to the first component and/or the second component. The current generator is operable to generate a current when the first component and the second component move with respect to each other in an engaged mode. A method for generating a current is also disclosed.
    Type: Application
    Filed: December 27, 2007
    Publication date: July 2, 2009
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Mark S. Grossman
  • Publication number: 20090172677
    Abstract: The present invention provides an efficient state management system for a complex ASIC, and applications thereof. In an embodiment, a computer-based system executes state-dependent processes. The computer-based system includes a command processor (CP) and a plurality of processing blocks. The CP receives commands in a command stream and manages a global state responsive to global context events in the command stream. The plurality of processing blocks receive the commands in the command stream and manage respective block states responsive to block context events in the command stream. Each respective processing block executes a process on data in a data stream based on the global state and the block state of the respective processing block.
    Type: Application
    Filed: December 22, 2008
    Publication date: July 2, 2009
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Michael MANTOR, Rex Eldon MCCRARY
  • Publication number: 20090172370
    Abstract: One or more processor cores of a multiple-core processing device each can utilize a processing pipeline having a plurality of execution units (e.g., integer execution units or floating point units) that together share a pre-execution front-end having instruction fetch, decode and dispatch resources. Further, one or more of the processor cores each can implement dispatch resources configured to dispatch multiple instructions in parallel to multiple corresponding execution units via separate dispatch buses. The dispatch resources further can opportunistically decode and dispatch instruction operations from multiple threads in parallel so as to increase the dispatch bandwidth. Moreover, some or all of the stages of the processing pipelines of one or more of the processor cores can be configured to implement independent thread selection for the corresponding stage.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Michael Gerard Butler
  • Patent number: 7553732
    Abstract: A method for constraining lateral growth of gate caps formed during an epitaxial silicon growth process to achieve raised source/drain regions on poly silicon is presented. The method is appropriate for integration into a manufacturing process for integrated circuit semiconductor devices. The method utilizes selective etch processes, dependant upon the material comprising the protective layer (hard mask) over the gate and the material of the spacers, e.g., oxide mask/nitride spacers, or nitride mask/oxide spacers.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: June 30, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David E. Brown, Scott D. Luning
  • Patent number: 7555633
    Abstract: Various embodiments of methods and systems for implementing a microprocessor that fetches a group of instructions into instruction cache in response to a corresponding trace being evicted from the trace cache are disclosed. In some embodiments, a microprocessor may include an instruction cache, a trace cache, and a prefetch unit. In response to a trace being evicted from trace cache, the prefetch unit may fetch a line of instructions into instruction cache.
    Type: Grant
    Filed: November 3, 2003
    Date of Patent: June 30, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gregory William Smaus, Mitchell Alsup
  • Publication number: 20090160867
    Abstract: Embodiments directed to an autonomous graphics processing unit (GPU) scheduler for a graphics processing system are described. Embodiments include an execution structure for a host CPU and GPU in a computing system that allows the GPU to execute command threads in multiple contexts in a dynamic rather than fixed order based on decisions made by the GPU. This eliminates a significant amount of CPU processing overhead required to schedule GPU command execution order, and allows the GPU to execute commands in an order that is optimized for particular operating conditions. The context list includes parameters that specify task priority and resource requirements for each context. The GPU includes a scheduler component that determines the availability of system resources and directs execution of commands to the appropriate system resources, and in accordance with the priority defined by the context list.
    Type: Application
    Filed: December 19, 2007
    Publication date: June 25, 2009
    Applicant: Advance Micro Devices, Inc.
    Inventor: Mark S. Grossman
  • Publication number: 20090161773
    Abstract: Methods and apparatus, including computer program products, are provided for channel estimation. In one aspect, there is provided a receiver including a demodulator for decoding a signal including at least one of a transmission parameter signaling (TPS) carrier and a data carrier. The receiver further includes a channel estimator, coupled to the demodulator, for determining a channel estimate for the TPS carrier. Moreover, the receiver includes an interpolator, coupled to the channel estimator, for determining, based on the determined channel estimate for the TPS carrier, another channel estimate for the data carrier. Related systems, methods, and articles of manufacture are also disclosed.
    Type: Application
    Filed: December 20, 2007
    Publication date: June 25, 2009
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Ravikiran Rajagopal
  • Publication number: 20090164726
    Abstract: Methods and systems for processing memory lookup requests are provided. In an embodiment, an address processing unit includes an instructions module configured to store instructions to be executed to complete a primary memory lookup request and a logic unit coupled to the instructions module. The primary memory lookup request is associated with a desired address. Based on an instruction stored in the instructions module, the logic unit is configured to generate a secondary memory lookup request that requests the desired address. In another embodiment, a method of processing memory lookups requests includes receiving a primary memory lookup request that corresponds to a desired memory address and generating a plurality of secondary memory lookup requests.
    Type: Application
    Filed: December 20, 2007
    Publication date: June 25, 2009
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Stanislaw K. SKOWRONEK
  • Publication number: 20090160865
    Abstract: Embodiments of the invention as described herein provide a solution to the problems of conventional methods as stated above. In the following description, various examples are given for illustration, but none are intended to be limiting. Embodiments include a frame processor module in a graphics processing system that examines the intra-coded and inter-coded frames in an encoded video stream and initiates migration of decoding and rendering functions to a second graphics processor from a first graphics processor based on the location of intra-coded frames in a video stream and the composition of intermediate inter-coded frames.
    Type: Application
    Filed: December 19, 2007
    Publication date: June 25, 2009
    Applicant: Advance Micro Devices, Inc.
    Inventor: Mark S. Grossman