Patents Assigned to Advanced Micro Devices
  • BODY TIE TEST STRUCTURE FOR ACCURATE BODY EFFECT MEASUREMENT
    Publication number: 20090101976
    Abstract: A body tie test structure and methods for its manufacture are provided. The transistor comprises a body-tied semiconductor on insulator (SOI) transistor formed in a layer of semiconductor material, the transistor comprising a cross-shaped gate structure with a substantially constant gate length L. An insulating blocking layer enables formation of a spacer region in the layer of semiconductor material separating the source and drain regions from the body tie region. A conductive channel with substantially the same inversion characteristics as the intrinsic transistor body connects the body tie to the intrinsic transistor body through the spacer region.
    Type: Application
    Filed: October 18, 2007
    Publication date: April 23, 2009
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Sriram MADHAVAN, Qiang CHEN, Darin A. CHAN, Jung-Suk GOO
  • Method for forming integrated circuit
    Patent number: 7521304
    Abstract: A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: April 21, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Richard J. Huang, Scott A. Bell, Srikanteswara Dakshina-Murthy, Philip A. Fisher, Richard C. Nguyen, Cyrus E. Tabery, Lu You
  • Methods for fabricating a stress enhanced semiconductor device having narrow pitch and wide pitch transistors
    Patent number: 7521380
    Abstract: A method is provided for fabricating a semiconductor device on a semiconductor substrate. A plurality of narrow gate pitch transistors (NPTs) and wide gate pitch transistors (WPTs) are formed on and in the semiconductor substrate. The NPTs are spaced apart by a first distance, and the WPTs are spaced apart by a second distance greater than the first distance. A first stress liner layer is deposited overlying the NPTs, the WPTs and the semiconductor layer, an etch stop layer is deposited overlying the first stress liner layer, and a second stress liner layer is deposited overlying the etch stop layer. A portion of the second stress liner layer which overlies the WPTs is covered, and an exposed portion of the second stress liner layer which overlies the NPTs is removed to expose an exposed portion of the etch stop layer. The exposed portion of the etch stop layer which overlies the NPTs is removed.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: April 21, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andrew M. Waite, Scott Luning, Frank (Bin) Yang
  • Ultra-low power crystal oscillator
    Patent number: 7522010
    Abstract: An ultra-low power crystal oscillator architecture that draws less than 2 ?A during steady state operation. An amplifier stage is self biased and has input and output clamp circuits that limit its signal swing. Circuit values are selected such that there is sufficient transient load current for the first amplifier stage to oscillate, while at the same time the input and output clamp circuits maintain a sufficiently low swing of the stage such that the steady state average load current is on the order of less than 1 ?A.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: April 21, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kevin YiKai Liang, Arvind Bomdica, Min Xu, Ming So
  • Output buffer with slew rate control utilizing an inverse process dependent current reference
    Patent number: 7521975
    Abstract: An output driver circuit provides more constant slew rates in the presence of process, voltage, or temperature variations that affect performance. An open ended (no feedback) solution is utilized that provides more constant slew rates in spite of PVT variations. A first performance dependent current and a reference current are generated and a third current is generated that is inversely related to performance utilizing the reference current and the performance dependent current. The third current is supplied to a gate of a first transistor circuit forming a portion of the output driver to thereby control the slew rate.
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: April 21, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Randall Paul Biesterfeldt, Bryan Timothy Heenan
  • Method of forming a metal layer over a patterned dielectric by wet chemical deposition including an electroless and a powered phase
    Patent number: 7517782
    Abstract: By performing an electroless deposition and an electro deposition process in situ, highly reliable metallizations may be provided, wherein limitations with respect to contaminations and device scaling, encountered by conventional chemical vapor deposition (CVD), atomic layer deposition (ALD) and physical vapor deposition (PVD) techniques for the formation of seed layers may be overcome. In some embodiments, a barrier layer is also deposited on the basis of a wet chemical deposition process.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: April 14, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Axel Preusse, Susanne Wehner, Markus Nopper
  • Method of configuring a system and system therefor
    Patent number: 7519883
    Abstract: A first scan data is received at a first scan chain and a representation of the first scan data is subsequently provided from the first scan chain to a second scan chain to test the second scan chain in response to a first value at a first bond pad. The first scan chain is bypassed to receive the first scan data at the second scan chain in response to a second value at the first bond pad.
    Type: Grant
    Filed: April 5, 2005
    Date of Patent: April 14, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Daniel E. Daugherty, Brett A. Tischler, Steven J. Kommrusch
  • Arrangement in a channel adapter for transmitting data according to link widths selected based on received link management packets
    Patent number: 7519089
    Abstract: A channel adapter, configured for sending frame data according to link widths selected based on management frames received from a link partner, includes a multiplexer circuit configured for selectively switching the frame data supplied according a prescribed maximum link width, to one of a plurality of available link widths for a transmit bus, and a bus controller. The bus controller is configured for controlling the multiplexer circuit to switch the frame data to one of the available link widths, including the prescribed link width, based the selected link width. Hence, a channel adapter can be configured for an optimum link width for communication with a corresponding channel adapter on a peer node.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: April 14, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Joseph Winkles, Joseph A. Bailey
  • Burn-in using system-level test hardware
    Patent number: 7519880
    Abstract: A burn-in test system. A burn-in test system includes a device under test (DUT), a temperature controller coupled to the DUT, and a test controller. During testing, the test controller: (a) sets a parameter of the DUT to a first value and applies a test stimulus to the DUT, and (b) sets the parameter of the DUT to a second value and applies the test stimulus to the DUT. A change in the value of the parameter results in a change in the amount of heat dissipated by the DUT. The temperature controller maintains the DUT at a pre-determined temperature during testing with the parameter set to both the first and the second values. The DUT may be further coupled to a module that comprises circuitry employed in a product-level application environment. The module is configured by the test controller to simulate a product-level application.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: April 14, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Trent William Johnson, Steven Russell Klassen, Jeff Brinkley, Glenn Eubank, John Heon Yi, Satwant Singh, Michael Gregory Tarin, Chandrakant Pandya
  • Metal cage structure and method for EMI shielding
    Patent number: 7518067
    Abstract: According to one exemplary embodiment, a structure comprises an electronic device situated over a substrate of a semiconductor die. The structure further includes a metal cage comprising a number of contacts situated over the substrate and surrounding the electronic device. The contacts form a lateral EMI shield portion of the metal cage. The structure also includes a number of vias connecting a number of metal interconnect segments to the contacts. The metal interconnect segments form a top EMI shield portion of the metal cage.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: April 14, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mayank Gupta, Mario Pelella, Farzin Assad
  • Method and apparatus for integrating multiple sample plans
    Patent number: 7519447
    Abstract: The present invention provides a method and apparatus for integrating multiple sample plans. The method includes receiving a first wafer state data set from an in situ wafer measurement device, the first wafer state data set being indicative of at least one characteristic of at least one wafer processed by a processing tool and receiving a second wafer state data set from an ex situ wafer measurement device, the second wafer state data set being indicative of the at least one characteristic of the at least one wafer processed by the processing tool. The method also includes forming a third wafer state data set using the first and second wafer state data sets and determining the at least one characteristic of the at least one wafer based upon the third wafer state data set.
    Type: Grant
    Filed: October 5, 2004
    Date of Patent: April 14, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christopher A. Bode, Kevin R. Lensing
  • Technique for creating different mechanical stress in different channel regions by forming an etch stop layer having differently modified intrinsic stress
    Patent number: 7517816
    Abstract: By providing a contact etch stop layer, the stress in channel regions of different transistor types may be effectively controlled, wherein tensile and compressive stress portions of the contact etch stop layer may be obtained by well-established processes, such as wet chemical etch, plasma etch, ion implantation, plasma treatment and the like. Hence, a significant improvement in transistor performance may be obtained while not significantly contributing to process complexity.
    Type: Grant
    Filed: February 15, 2005
    Date of Patent: April 14, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kai Frohberg, Matthias Schaller, Massud Aminpur
  • Combined command and response on-chip data interface for a computer system chipset
    Patent number: 7519755
    Abstract: An integrated circuit chip, particularly a southbridge, is provided that has a first and a second circuit unit. Each circuit unit can send requests to the other one and send back a response when receiving a request that requires a response. The first circuit unit is connected to the second circuit unit to send to the second circuit unit request data relating to a request to be sent by the first circuit unit and response data relating to a response to be sent by the first circuit unit over a shared signal line.
    Type: Grant
    Filed: October 14, 2004
    Date of Patent: April 14, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thomas Kunjan, Joerg Winkler, Frank Barth
  • TWO-STEP SIMULATION METHODOLOGY FOR AGING SIMULATIONS
    Publication number: 20090094013
    Abstract: The present invention is a method and system for simulating the aging process of a circuit. A two-step process is employed whereby, in a first simulation step, a simulation is conducted to obtain node voltages for the original circuit and the node voltages are stored in a file. In the second step, a subsequent simulation is run after transistors of the circuit are replaced by aging subcircuits, which contain aging models, and initial node voltages are updated. A script is used to set the bias voltage inputs for the aging models using the node voltages stored in the file from the first step. With more accurate bias voltage inputs for the aging models, the aging simulations are conducted to compute the circuit degradation.
    Type: Application
    Filed: October 9, 2007
    Publication date: April 9, 2009
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Rasit O. TOPALOGLU, Jung-Suk Goo
  • Circuit lid with a thermocouple
    Patent number: 7513686
    Abstract: Various devices for measuring an electronic device lid are provided. In one aspect, an apparatus is provided that includes an integrated circuit, a lid for positioning on the integrated circuit, and a junction of two dissimilar metals associated with the lid. The junction provides a thermocouple to provide an output signal representative of a temperature of the lid.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: April 7, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Joseph M. Schaffer
  • Systems and methods for communicating in a discrete multitone system
    Patent number: 7515640
    Abstract: A system for communicating in a discrete multitone system includes a transmitting station and a receiving station. The transmitting station transmits redundant sets of data on each of a number of different tones. The receiving station receives the redundant sets of data and identifies the data represented by the redundant sets of data using a voting scheme, such as a majority voting scheme.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: April 7, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Maged F. Barsoum, Fred Berkowitz
  • Method of integrated circuit packaging
    Patent number: 7513035
    Abstract: Various integrated circuit package elements are provided. In one aspect, an integrated circuit package device is provided that includes a lid for covering an integrated circuit. The lid has a convex surface for applying pressure on the integrated circuit when the lid is placed in a selected position. In another aspect, an integrated circuit package device is provided that includes a lid that has a surface for applying pressure to an integrated circuit when the lid is in a selected position. A gold film is coupled to the surface. The gold film has a periphery and a plurality of rounds extending from the periphery.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: April 7, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Seah Sun Too, Mohammad Khan, James Hayward, Jacquana Diep
  • Avoiding silent data corruption and data leakage in a virtual environment with multiple guests
    Patent number: 7516247
    Abstract: In an embodiment, an input/output memory management unit (IOMMU) is configured to receive a completion wait command defined to ensure that one or more preceding invalidation commands are completed by the IOMMU prior to a completion of the completion wait command. The IOMMU is configured to respond to the completion wait command by delaying completion of the completion wait command until: (1) a read response corresponding to each outstanding memory read operation that depends on a translation entry that is invalidated by the preceding invalidation commands is received; and (2) the control unit transmits one or more operations upstream to ensure that each memory write operation that depends on the translation table entry that is invalidated by the preceding invalidation commands has at least reached a bridge to a coherent fabric in the computer system and has become visible to the system.
    Type: Grant
    Filed: August 11, 2006
    Date of Patent: April 7, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark D. Hummel, Andrew W. Lueck, Geoffrey S. Strongin, Mitchell Alsup, Michael J. Haertel
  • Intra Motion Prediction for Response Time Compensation
    Publication number: 20090087108
    Abstract: An apparatus for a response time compensation system includes a plurality of complexity modules and a motion vector module. The complexity modules determine a plurality of complexity values based on current image information and prior image information. The motion vector module determines a desired complexity value based on a lowest of complexity values. The motion vector determines a desired motion vector based on the lowest of the plurality of complexity values. The desired complexity value and the desired motion vector are used to compress the current image information into a compressed bitstream. The compressed bitstream is used by the response time compensation system to provide display element response time compensation information for a display.
    Type: Application
    Filed: September 28, 2007
    Publication date: April 2, 2009
    Applicant: Advanced Micro Devices
    Inventor: Allen J.C. Porter
  • Memory Word Line Driver Featuring Reduced Power Consumption
    Publication number: 20090086563
    Abstract: Embodiments of a random access memory word line driver circuit that reduces consumption of standby power are described. The word line driver is based on NOR-gate logic in which, for memory array consisting of a plurality of memory cells and word line drivers, given two inputs selected one word line goes high and the rest remain zero. The decoder circuit comprises two PMOS transistors in series with an NMOS-based inverter circuit. This arrangement reduces the leakage current through the NMOS transistor when the word line is not selected. An array of word line drivers incorporating a NOR-based decoder includes a shared pull up PMOS transistor for one of two address lines. The shared pull-up PMOS transistor is manufactured to a size on the order of at least two times the width of the remaining transistors of each word line stage.
    Type: Application
    Filed: October 1, 2007
    Publication date: April 2, 2009
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Stephen L. Morein