Abstract: A method and apparatus for selectively executing an I/O instruction. The method includes creating an I/O permission bitmap in a memory and receiving an I/O port number and a security context identification (SCID) value. The method also includes using the SCID value and the I/O port number to access the I/O permission bitmap stored to obtain a permission bit corresponding to the I/O port and executing the I/O instruction dependent upon a value of the permission bit corresponding to the I/O port. The I/O permission bitmap includes a plurality of permission bits. Each of the permission bits corresponds to a different one of a plurality of I/O ports. Each of the permission bits has a value indicating whether access to the corresponding I/O port is allowed. The I/O port number indicates the I/O port referenced by the I/O instruction. The SCID value indicates a security context level of a memory location including the I/O instruction.

Abstract: The present invention provides a new technology approach for forming a contact layer in a microelectronic chip, which includes a plurality of solder bumps that are directly to be connected with a correspondingly designed carrier substrate. In the process flow, a plasma-based process for patterning the underbump metallization layer is used in combination with testing and assembling the device, thereby providing a high degree of process flexibility and/or cost reduction and/or device performance.

Abstract: Accurate ultrafine patterns are formed using a multiple exposure technique comprising implementing an OPC procedure to form an exposure reticle to compensate for distortion of an overlying resist pattern caused by an underlying resist pattern. Embodiments include forming a first resist pattern in a first resist layer over a target layer using a first exposure reticle, forming a second exposure reticle by an OPC technique to compensate for distortion of a second resist pattern caused by the underlying first resist pattern, depositing a second resist layer on the first resist pattern, forming the second resist pattern in the second resist layer using the second exposure reticle, the first and second resist patterns constituting a final resist mask, and forming a pattern in the target layer using the final resist mask.

Abstract: A processing node that is integrated onto a single integrated circuit chip includes a first processor core and a second processor core. The processing node also includes an operating system executing on either of the first processor core and the second processor core. The operating system may monitor a current utilization of the first processor core and the second processor core. The operating system may cause the first processor core to operate at performance level that is lower than a system maximum performance level and the second processor core to operate at performance level that is higher than the system maximum performance level in response to detecting the first processor core operating below a utilization threshold.

Abstract: The present disclosure relates to an integrated circuit packaging, a strip having a plurality of integrated circuit packages, and method of manufacture thereof, and more particularly, to a substrate having an integrated overhang support structure to support a ledge created by stacking a large circuit die on a small circuit die. In one embodiment, the upper substrate surface comprises a protrusion as an integrated support structure. The structure may include passages to direct the flow of underfill into the limited support area to create an open area for vacuum or for placement of passive or active components.

Abstract: Execution of the first thread of a new program is prioritized ahead of older threads for a previously running program. The new program is invoked during the execution of a thread of the previous program. The first thread of the program is prioritized ahead of the remaining threads of the previous program. In an embodiment of the invention, additional threads of the new program are also prioritized ahead of the older threads. A thread's context may include a table of constant values that can be referenced by each program and are shared by multiple threads. Changing the values in a constant table for a new thread is time intensive. To avoid changes to the constant table (and thereby save time), a higher priority status is conferred to the first thread that follows a change to the constant table.

Abstract: A composite exposure image is formed on a photoresist layer by applying a light beam through a reticle to form a first exposure image thereon, and thereafter, while maintaining the position of the reticle with respect to the photoresist layer, again applying a light beam through the reticle to form a second exposure image thereon. By adjusting the light beam differently in focus and intensity for each exposure, the combination of first and second exposure images form a pattern on the photoresist of lesser pitch than can be produced from a single exposure. The formation of a single pattern in the single resist layer from the two exposures avoids misalignment problems and eliminates the need for double exposure of a plurality of resist layers.

Abstract: By determining a metric for tool utilization in a manufacturing environment on the basis of tool-specific characteristics and a probability distribution for the transport capability of an automated material handling system, the influence of the transport system on the tool performance may be effectively determined. For this purpose, an average delay caused by the automated material handling system may be iteratively calculated on the basis of a respective required carrier exchange time, which depends on tool- and process-specific characteristics. From the corresponding average delay, an appropriate metric, such as a utilization loss factor, may be determined.

Abstract: According to one exemplary embodiment, a method for increasing manufacturability of a circuit layer includes determining a threshold value for at least one image property from a repetitive section of the circuit layout. According to this embodiment, the method further includes performing a simulated lithographic process using the circuit layout to determine a number of simulated values of the at least one image property for a non-repetitive section of the circuit layout. The method further includes comparing each of the simulated values with the threshold value to determine printability of the non-repetitive section of the circuit layout prior to lithographically printing the circuit layout on a wafer. The method further includes modifying the non-repetitive section of the circuit layout if the threshold value is greater than at least one of the simulated values. By modifying the non-repetitive section of the circuit layout, manufacturability of the circuit layout can be increased.

Abstract: Methods are disclosed for forming self-aligned dual stressed layers for enhancing the performance of NFETs and PFETs. In one embodiment, a sacrificial layer is used to remove a previously deposited stressed layer. A mask position used to pattern the sacrificial layer is adjusted such that removal of the latter deposited stressed layer, using the sacrificial layer, leaves the dual stress layers in an aligned form. The methods result in dual stressed layers that do not overlap or underlap, thus avoiding processing problems created by those issues. A semiconductor device including the aligned dual stressed layers is also disclosed.

Abstract: A method of forming a silicon-on-insulator semiconductor device including providing a substrate, forming an insulating layer on the substrate, forming a process layer on the insulating layer, implanting ions into the process layer adjacent the insulating layer, and forming a strained silicon layer over the process layer. Implanting ions into the process layer adjacent the insulating layer reduces floating body effects of the semiconductor device, while the strained silicon layer covers surface defects form by the implanted ions in the process layer to enhance mobility of the semiconductor device.

Abstract: The present invention provides a technique for forming differently stressed contact etch stop layers, wherein sidewall spacers are removed prior to the formation of the contact etch stop layers. During the partial removal of respective contact etch stop layers, a corresponding etch stop layer regime is used to substantially avoid any unwanted stress-inducing material residuals, thereby significantly enhancing the stress transfer mechanism.

Abstract: A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).

Abstract: Double-sided waffle packs and methods of using the same are provided. In one aspect, a waffle pack is provided that includes a body that has a first side and second side opposite the first side. The first side has a first cavity for enabling a semiconductor die to be seated therein when the body is in a first orientation. The second side has a second cavity for enabling a semiconductor die to be seated therein when the body is in a second orientation opposite the first orientation. The first cavity has a first footprint and the second cavity has a second footprint. The first and second footprints are substantially aligned vertically.

Abstract: Ultrafine dimensions, smaller than conventional lithographic capabilities, are formed employing an efficient inverse spacer technique comprising selectively removing spacers. Embodiments include forming a first mask pattern over a target layer, forming a spacer layer on the upper and side surfaces of the first mask pattern leaving intermediate spaces, depositing a material in the intermediate spacers leaving the spacer layer exposed, selectively removing the spacer layer to form a second mask pattern having openings exposing the target layer, and etching the target layer through the second mask pattern.

Abstract: In one embodiment, an input/output memory management unit (IOMMU) comprises a cache to cache translation data from memory; and a control unit coupled to the cache. The control unit is configured to implement address translation and memory protection for memory requests sourced by one or more input/output (I/O) devices. The memory requests sourced by the I/O devices travel in one or more first virtual channels, and the control unit is configured to transmit memory requests sourced by the control unit in at least a second virtual channel separate from the first virtual channels.

Abstract: Ultrafine dimensions are accurately and efficiently formed in a target layer using a spacer lithographic technique comprising forming a first mask pattern, forming a cross-linkable layer over the first mask pattern, forming a cross-linked spacer between the first mask pattern and cross-linkable layer, removing the cross-linkable layer, cross-linked spacer from the upper surface of the first mask pattern and the first mask pattern to form a second mask pattern comprising remaining portions of the cross-linked spacer, and etching using the second mask pattern to form an ultrafine pattern in the underlying target layer.

Abstract: The present invention allows correcting malfunctions occurring in the formation of a cap layer on an electrical element in a semiconductor substrate. It is detected whether a malfunction occurred in the formation of the cap layer. If a malfunction in the formation of the cap layer was detected, a rework procedure is performed. The rework procedure can comprise exposing the substrate to a first acid and a second acid.

Abstract: A method of forming a contact through a material includes forming a via through a dielectric material and cleaning the via using a dilute hydrofluoric (DHF) acid solution. The method further includes depositing a barrier layer within the via and depositing metal adjacent the barrier layer.

Abstract: By providing a barrier layer stack including a silicon nitride layer for confining a copper-based metal region, thereby also effectively avoiding any diffusion of oxygen and moisture into the copper region, and a nitrogen-enriched silicon carbide layer, the total relative permittivity may be maintained at a low level, since the thickness of the silicon nitride layer may be moderately thin, while the relatively thick silicon carbide nitride layer provides the required high etch selectivity during a subsequent patterning process of the low-k dielectric layer.