Abstract: A method, apparatus, and a system for generating an index for storing data. A pattern associated with a first set of data is determined. The first set of data is stored. A determination is made as to whether the pattern associated with a second set of data corresponds to the pattern associated with the first set of data. An index associated with the first set of data is correlated to the second set of data in response to determining that the pattern associated with the second set of data corresponds to the pattern associated with the first set of data.

Abstract: By omitting a growth mask or by omitting lithographical patterning processes for forming growth masks, a significant reduction in process complexity may be obtained for the formation of different strained semiconductor materials in different transistor types. Moreover, the formation of individually positioned semiconductor materials in different transistors may be accomplished on the basis of a differential disposable spacer approach, thereby combining high efficiency with low process complexity even for highly advanced SOI transistor devices.

Abstract: A method and apparatus are provided for initiating test runs based on a fault detection result. The method comprises receiving operational data associated with processing of a workpiece by a processing tool, processing the operational data to determine fault detection results; and causing a test run to be performed based on at least a portion of the fault detection results.

Abstract: Security processing circuits are discussed which may be used alone or as part of a network interface device of a host system using a single DES engine to accomplish 3DES processing. The security processing circuit is adapted for selectively encrypting outgoing data and decrypting incoming data, where the network interface device may be fabricated as a single integrated circuit chip. Methods are also provided for performing 3DES encryption and decryption services between the host system and a network, in which security information is obtained from the host system, which is used together with a set of secret keys for 3DES processing data utilizing a single DES engine and an intermediate result fed back to the single DES engine of the 3DES IPsec circuit.

Abstract: A device and method for interpolation during frame rate conversion are disclosed. The method includes, receiving original frames Fn and Fn+1 to interpolate a new frame Fp between the original frames. The method involves forming candidate motion vectors describing possible motion trajectories for groups of pixels between Fn and Fn+1 respectively, and selecting actual motion vectors from the candidate vectors. Each motion vector is selected with respect to a group of pixel locations in the new frame Fp to be interpolated. The device includes a motion estimator, an interpolator and a correction engine. Motion vectors are computed by the estimator, while the new frame is interpolated by the interpolator using motion compensated interpolation. The motion vectors are further used to identify regions of halo artifacts in the interpolated frame and filtering is applied by the correction engine to reduce the halo artifacts.

Abstract: A method of detecting damage to at least one dielectric layer in an IC die by determining a capacitance factor. The capacitance factor can be used to determine damage in a low-k dielectric material. A system for detecting damage can include a conductive line structure for measuring capacitance and software or a device for determining the capacitance to determine the damage.

Abstract: Video control signals are received at a video input port of a system. A determination is made whether the video control signals are valid or invalid. When video control signals represent a valid video signal, providing a delayed representation of a control signal to a synchronization input of a display engine of the system, and when the video control signals represent an invalid video signal, providing a an alternative signal to the synchronization input of the display engine.

Abstract: A semiconductor device is disclosed having a conductive gate structure overlying a semiconductor layer having a major surface. An isolation material is recessed within a trench region below the major surface of the semiconductor layer. An epitaxial layer is formed overlying a portion of the major surface and on an active region forming a sidewall of the trench.

Abstract: By directly forming an underbump metallization layer on a copper-based contact region, the formation of any other terminal metals, such as aluminum and corresponding adhesion/barrier layers may be avoided. Consequently, the thermal and electrical behavior of the resulting bump structure may be improved, while process complexity may significantly be reduced.

Abstract: By enabling an interleaved mode when supplying substrates from a plurality of load ports to a respective process module, a reduction of non-productive time of the process tool and/or a reduction of cycle time may be achieved compared to a conventional sequential processing of carriers. Upon arrival at a load port of the process tool, an appropriate priority may be assigned to the carrier, wherein a higher priority may enable the interruption of the processing of a lower-ranked substrate carrier.

Abstract: A method and apparatus for controlling access to segments of memory having security data stored therein is provided. A security check unit maintains information for a plurality of segments of memory regarding whether each of these plurality of segments has secure data stored therein. A hint directory maintains information regarding whether any of a plurality of these segments has secure data stored therein. The hint directory is capable of bypassing the security check unit when it receives an address that falls within a plurality of the segments that have been indicated as being free from secure data. When the hint directory determines that a received address falls within one of a plurality of segments that contain secure data, then the address is passed to the security check unit for a closer examination.

Abstract: By forming a semiconductor alloy in a silicon-based active semiconductor region prior to the gate patterning, material characteristics of the semiconductor alloy itself may also be exploited in addition to the strain-inducing effect thereof. Consequently, device performance of advanced field effect transistors may be even further enhanced compared to conventional approaches using a strained semiconductor alloy in the drain and source regions.

Abstract: The present invention generates model scenarios of semiconductor chip design and uses interpolation and Monte Carlo, with random number generation inputs, techniques to iteratively assess the models for a more comprehensive and accurate assessment of design space, and evaluation under projected manufacturing conditions. This evaluation information is then incorporated into design rules in order to improve yield.

Abstract: A model of the memory device is provided, including a memory array model having a plurality of memory array model locations, and a plurality of decoder models, each associated with a memory array model location. Each memory array model location includes a first data set accessed with the input to that memory array model location in a first state, and a second data set accessed with the input to that memory array model location in a second state. The memory device model is provided to an automatic test pattern generation (ATPG) tool, and a test pattern is generated based on the memory device model.

Abstract: To determine performance degradation at functional module in a normal power state due to a power control device, voltages are applied to oscillators at a power diagnostic module. A first voltage is a supply voltage for the data processing device, and a second voltage is a supply voltage applied at a functional module of the data processing device. Counters are adjusted based on the oscillators to determine the oscillators' respective frequencies. In addition, the power diagnostic module can include a timer to measure the length of time that the functional module is in a low-power state, and an analog to digital converter to measure the voltage applied to the functional module during transitions to and from the low-power state.

Abstract: By dynamically adapting the transport sequencing rules of a cluster tool, the overall performance of the tool may be increased. In some illustrative embodiments, the transport sequencing rule for a robot handler may be dynamically changed when a lot of small size is present in one of the load ports in order to increase the window of opportunity for carrier exchange of a standard lot size currently processed. Consequently, by reducing the overall process time for the currently processed lot while delaying the completion of the small lot, the currently processed carrier may be exchanged earlier, thereby reducing the overall cycle time of the currently processed lot and/or providing a next lot earlier to the tool.

Abstract: A technique of operating a processor includes determining whether a floating point unit (FPU) of the processor is to operate in a full-bit mode or a reduced-bit mode. An instruction is fetched and the instruction is decoded into a single operation, when the full-bit mode is indicated, or multiple operations, when the reduced-bit mode is indicated.

Abstract: A method includes defining a plurality of simple sampling rules for selecting material for metrology. Each simple sampling rule has an associated penalty. At least one combination sampling rule relating a subset of at least two simple sampling rules is defined. The combination sampling rule has an associated penalty. The penalties are assessed responsive to a previous material selection not satisfying the simple sampling rules or the combination sampling rule. Material is selected for subsequent metrology based on the sampling rules and the assessed penalties. At least one characteristic of the selected material is measured.

Abstract: By increasing the transistor topography after forming a first layer of highly stressed dielectric material, additional stressed material may be added, thereby efficiently increasing the entire layer thickness of the stressed dielectric material. The corresponding increase of device topography may be accomplished on the basis of respective placeholder structures or dummy gates, wherein well-established gate patterning processes may be used or wherein nano-imprint techniques may be employed. Hence, in some illustrative embodiments, a significant increase of strain may be obtained on the basis of well-established process techniques.

Abstract: A polyelectrolyte solution for tuning a surface energy and a method for using the polyelectrolyte solution to manufacture an integrated circuit. A substrate is provided and a photosensitive material having a surface energy is formed over the substrate. The substrate may be polysilicon, silicon dioxide, silicon nitride, metal, and the like. The photosensitive material is treated with a polyelectrolyte solution to change the surface energy of the photosensitive material. Treatment techniques for applying the polyelectrolyte solution may include spraying, bathing, rinsing, soaking, or washing. The polyelectrolyte adsorbs to the photosensitive material forming a polyelectrolyte polymer layer on the photosensitive material. The photosensitive material may be a photoresist or a photoresist having a topcoat formed thereon. The photosensitive material is exposed using lithography techniques and processed to form a patterned layer of photosensitive material for use in manufacturing the integrated circuit.