Abstract: Embodiments of a scannable IO circuit featuring reduced latch count for pipelined memory architectures and test methodology are described. For a pipelined memory system performing at speed tests, the timing sequence for processing a test command comprises a precharge-read-precharge-write sequence for each clock cycle starting with the rising clock edge. The memory circuit utilizing this test command timing sequence comprises a sense amplifier and a single latch. The sense amplifier itself is used as a latch to implements scan functionality for the memory circuit. The memory device is incorporated into an integrated test wrapper circuit that executes back-to-back commands through serial compare operations using integrated scan flip-flop circuits. The test wrapper includes a fanout block and padded address scheme for testing multiple and disparate size memory devices in parallel.

Abstract: An apparatus for response time compensation includes a compression module, a decompression module, a display element response time compensation module, and a bypass control module. The compression module compresses a current frame to produce a compressed previous frame of image information. The decompression module decompresses the compressed previous frame of image information to produce a decompressed previous frame of image information. The display element response time compensation module provides display compensation information for a display based on the current frame and the decompressed previous frame. The bypass control module causes the current frame information to selectively bypass the compression module, the decompression module, and/or the display element response time compensation module based on display mode information.

Abstract: An apparatus includes a control module and an activity module. The control module provides error control information based on a target number of bits and an actual number of bits required to pack at least one compressed block of image information. The activity module provides a quantization factor based on the error control information and a complexity value of the at least one compressed block of image information. The quantization factor is used to pack the at least one compressed block of image information into a bitstream comprising the target number of bits.

Abstract: Methods, systems and program products are disclosed for performing a stress test of a line in an integrated circuit (IC) chip. One embodiment of the method includes: applying a constant current Is to the line; and stress testing the line while applying the constant current Is such that the constant current Is is not altered by a resistance change due to an onset of electromigration.

Abstract: The invention relates to a network interface system for interfacing a host system with a network. The network interface system includes a bus interface system, a media access control system, and a security system. The security system is operative to selectively authenticate incoming and outgoing data. The security system includes a pipeline that masks mutable fields from incoming data prior to authentication.

Abstract: A strained semiconductor material may be positioned in close proximity to the channel region of a transistor, such as an SOI transistor, while reducing or avoiding undue relaxation effects of metal silicides and extension implantations, thereby providing enhanced efficiency for the strain generation.

Abstract: A method and apparatus for scheduling appointments in a manufacturing process flow are disclosed. The method and apparatus include a number of aspects including appointments in which processing windows float within commitment windows; appointments in which the processing windows include consumption and processing intervals and in which the processing windows can overlap with the processing interval of other appointments; the use of different kinds of calendars including different types of appointments maintained in a variety of states; a calendaring system in which appointments are constrained by the implicit constraints not represented by booked appointments as well as the explicit constraints represented by booked appointments; calendar manipulation techniques used in managing the calendars; and corresponding appointments maintained over multiple calendars in a synchronized manner.

Abstract: A system includes a memory operable to store scrambled data at a plurality of memory locations. The system also includes an empty detector operable to determine whether a specified memory location is empty using contents of the specified memory location. The contents of the specified memory location are not descrambled for use by the empty detector in determining whether the specified memory location is empty.

Abstract: A negative differential resistance (NDR) diode and a memory cell incorporating that NDR diode are provided. The NDR diode comprises a p-type germanium region in contact with an n-type germanium region and forming a germanium pn junction diode. A first gate electrode overlies the p-type germanium region, is electrically coupled to the n-type germanium region, and is configured for coupling to a first electrical potential. A second gate electrode overlies the n-type germanium region and is configured for coupling to a second electrical potential. A third electrode is electrically coupled to the p-type germanium region and may be coupled to the second gate electrode. A small SRAM cell uses two such NDR diodes with a single pass transistor.

Abstract: Multiple gate transistors are provided with a dual stress layer for increased channel mobility and enhanced effective and saturated drive currents. Embodiments include transistors comprising a first stress layer under the bottom gate and a second stress layer overlying the top gate. Embodiments further include transistors with the bottom gate within or through the first stress layer. Methodology includes sequentially depositing stressed silicon nitride, nitride, oxide, amorphous silicon, and oxide layers on a substrate having a bottom oxide layer thereon, patterning to define a channel length, depositing a top nitride layer, patterning stopping on the stressed silicon nitride layer, removing the amorphous silicon layer, epitaxially growing silicon through a window in the substrate to form source, drain, and channel regions, doping, removing the deposited nitride and oxide layers, growing gate oxides, depositing polysilicon to form gates, growing isolation oxides, and depositing the top stress layer.

Abstract: A circuit includes a high priority circuit and a non-high priority circuit. The high priority circuit is operative to communicate high priority information to a single path of a differential serial communication link. The non-high priority circuit communicates non-high priority information to the single path. The high priority information is communicated prior to the non-high priority information. In one example, the circuit includes a flow control distributor operatively coupled to the high priority circuit and the non-high priority circuit. The flow control distributor distributes a total number of flow control credits into high priority credits and non-high priority credits. The flow control distributor controls communication of the high priority information based on the high priority credits. The flow control distributor controls communication of the non-high priority information based on the non-high priority credits.

Abstract: A system including input offset correction for asymmetric control of high-speed bidirectional signaling includes a slave device and a master device that is coupled to the slave device. The master device may control data transfer between the master device and the slave device. In response to the master device determining there is an input offset bias present within the slave device, the master device may adaptively modify a DC voltage offset of data transmitted by the master device based upon data eye information received from the slave device via one or more unidirectional signal paths.

Abstract: A method and system for integrated circuit (IC) processing combines an ion implantation tool and a laser anneal tool in a single unit with a shared precision X-Y scanner. A semiconductor wafer is loaded onto a the X-Y table of the scanner. Data defining the desired ion implantation is used to first customize circuit areas on the semiconductor wafer by gating ON and OFF the ion beam while semiconductor wafer is scanned. Any inadvertent ion beam interruptions are noted by storing the locations of the interruptions. The wafer is then reprocessed to correct faults caused by the interruptions. The laser anneal tool positions the laser beam over the semiconductor wafer it is then scanned while gating the laser beam ON and OFF to custom anneal the wafer devices. Again, any inadvertent laser beam interruptions are detected and the locations of the interruptions are stored for reprocessing to correct faults.

Abstract: A method and system for efficiently managing power consumption in a mobile device controls power consumption with an adjustable sleep period or listening interval that may be user-specified and automatically tuned based on recent detected usage. With an adjustable sleep period, a receiver conserves power by leaving a sleep mode only at predefined and adjustable periods, which may be selected by the user to balance connectivity and power saving and which may be automatically incremented when the device activity is low.

Abstract: A system for phase tracking and equalization across a byte group for asymmetric control of high-speed bidirectional signaling includes a slave device and a master device that is coupled to the slave device via a plurality of bidirectional data paths. The master device may adaptively modify transmit characteristics based upon data eye information sent via one or more unidirectional data paths by the slave device. The data eye information may correspond to an edge position of data signal transitions received by the slave device on each data path of the plurality of bidirectional data paths. In addition, the master device may modify data path equalization coefficients within the master device for a grouping of the bidirectional data paths such as a byte group, for example, dependent upon the data eye information.

Abstract: A method is provided for fabricating a semiconductor device which includes a first contact point and a second contact point located above the first contact point. A first material layer is conformally deposited over the contact points, and a second material layer is deposited. A photoresist layer is applied and patterned to leave remaining portions. The remaining portions are trimmed to produce trimmed remaining portions which overlie eventual contact holes to the contact points. Using the trimmed remaining portions as an etch mask, exposed portions the second material layer are etched away to leave sacrificial plugs. The sacrificial plugs are etched away to form contact holes that reach portions the first material layers. Another etching step is performed to extend the contact holes to produce final contact holes that extend to the contact points.

Abstract: A stressed field effect transistor and methods for its fabrication are provided. The field effect transistor comprises a silicon substrate with a gate insulator overlying the silicon substrate. A gate electrode overlies the gate insulator and defines a channel region in the silicon substrate underlying the gate electrode. A first silicon germanium region having a first thickness is embedded in the silicon substrate and contacts the channel region. A second silicon germanium region having a second thickness greater than the first thickness and spaced apart from the channel region is also embedded in the silicon substrate.

Abstract: Methods are provided for enhancing resolution of a chemically amplified photoresist. A film comprising a photoacid generator and a polymer comprising functional groups bonded to protecting moieties is deposited on a substrate. The film is exposed to patterned radiation. The patterned radiation results in protonation of a portion of the functional groups and the formation of a latent image within the film. The bonds between the protonated functional groups and the protecting moieties are selectively excited with non-thermal energy having a wavelength spectrum that resonantly cleaves the bonds.

Abstract: A USB (Universal Serial Bus) OTG (On-The-Go) controller device and more generally a serial bus control circuit chip are provided which have improved port handler implementations. In one example, different port handler units may be provided which selectively support host and device functionality at the respective ports. In another example, a first port handler for providing host functionality and a second port handler for providing device functionality are provided which are of substantially the same hardware structure. In a further example, at least one port handler is provided that has a low level protocol module for handling packet assembly and/or disassembly, a transfer buffer module for buffering incoming or outgoing data to average out system memory latencies, and a memory access module for generating memory requests in compliance with host and/or device functionality.

Abstract: A method is provided for fabricating a memory device. A semiconductor substrate is provided which includes a first well region having a first conductivity type, a second well region having the first conductivity type, a first gate structure overlying the first well region and the second gate structure overlying the second well region. An insulating material layer is conformally deposited overlying exposed portions of the semiconductor substrate. Photosensitive material is provided over a portion of the insulating material layer which overlies a portion of the second well region. The photosensitive material exposes portions of the insulating material layer. The exposed portions of the insulating material layer are anisotropically etched to provide a sidewall spacer adjacent a first sidewall of the second gate structure, and an insulating spacer block formed overlying a portion of the second gate structure and adjacent a second sidewall of the second gate structure.