Abstract: A plurality of channels are formed in a base, e.g., a substrate of an integrated circuit, each channel extending between edges of the base. Two pairs of manifolds are provided, the first pair communicating with a first group of channels and the second pair communicating with a second group of channels, the first group of channels and the first pair of plena isolated from the second group of channels and the second pair of plena. Each of the pairs of manifolds includes multiple branches coupled to the channels and a common plenum. Cooling fluid is injected into the channels from different sides of the base, causing fluid to flow in different directions in the two groups of channels, the channels in thermal contact with the integrated circuit.

Abstract: A memory access technique is provided that may be used in WLAN (Wireless Local Area Network) communication devices. An on-chip memory has multiple memory circuits forming individually addressable memory segments. An arbitration unit arbitrates between multiple requesters, each requesting access to the on-chip memory. The requesters are on-chip circuits and/or external devices. The arbitration unit determines a memory circuit to be accessed for each request that is received from a requester. The determination may be based on a software configurable arbitration scheme. The memory segments may form a bank of single-port SRAM (Static Random Access Memory) devices.

Abstract: A method for processing workpieces in a process flow including a plurality of operations includes employing a fabrication simulation model of the process flow to determine an estimated completion time for a selected workpiece. The fabrication simulation model simulates the processing of the selected workpiece and other workpieces in the process flow through the plurality of operations. The priority of the selected workpiece is adjusted based on a comparison between a target completion time for the selected workpiece and the estimated completion time.

Abstract: The present invention provides a method and apparatus for selecting wafers for sampling. The method includes determining a plurality of sampling rules associated with at least one of a plurality of wafers and selecting at least one wafer for sampling based on the plurality of sampling rules.

Abstract: A method for controlling an etch process comprises providing a wafer having at least a first layer and a second layer formed over the first layer. The thickness of the second layer is measured. An etch selectivity parameter is determined based on the measured thickness of the second layer. An operating recipe of an etch tool is modified based on the etch selectivity parameter. A processing line includes an etch tool, a first metrology tool, and a process controller. The etch tool is adapted to etch a plurality of wafers based on an operating recipe, each wafer having at least a first layer and a second layer formed over the first layer. The first metrology tool is adapted to measure a pre-etch thickness of the second layer. The process controller is adapted to determine an etch selectivity parameter based on the measured pre-etch thickness of the second layer and modify the operating recipe of the etch tool based on the etch selectivity parameter.

Abstract: Stressed MOS devices and methods for their fabrication are provided. The stressed MOS device comprises a T-shaped gate electrode formed of a material having a first Young's modulus. The T-shaped gate electrode includes a first vertical portion and a second horizontal portion. The vertical portion overlies a channel region in an underlying substrate and has a first width; the horizontal portion has a second greater width. A tensile stressed film is formed overlying the second horizontal portion, and a material having a second Young's modulus less than the first Young's modulus fills the space below the second horizontal portion. The tensile stressed film imparts a stress on the horizontal portion of the gate electrode and this stress is transmitted through the vertical portion to the channel of the device. The stress imparted to the channel is amplified by the ratio of the second width to the first width.

Abstract: A method of transmitting information in a WLAN (Wireless Local Area Network) network and corresponding WLAN communication devices and integrated circuit chips are provided. A correction signal is used for compensating for a dc offset in a data signal containing at least part of the information to be transmitted. The correction signal is varied by making it taking different values. For each of the different values, a strength of an indicator signal indicative of the dc offset is determined. Based upon the determined strength, an optimum value of the correction signal is identified at which the dc offset is minimized. The value of the correction signal is set to the optimum value. Further, a method of transmitting information in a WLAN network is provided, including compensating for a first and second dc offset in a first and second data signal, respectively, using a first and second feedback loop, respectively.

Abstract: A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer structure from a subsequent cleaning process. An epitaxial layer is formed subsequent to the cleaning process.

Abstract: A method and apparatus for temperature sensing in an IC. The IC includes a plurality of remote temperature sensors each coupled to a control logic unit. The plurality of remote temperature sensors may be distributed throughout the integrated circuit. The integrated circuit includes a reference unit coupled to provide a reference temperature to the control logic unit and a reference sensor coupled to provide a signal having a reference frequency to the control logic unit. The reference unit and the reference sensor are located near each other. The control logic unit is configured to correlate the reference frequency received from the reference sensor with the reference temperature received from the reference unit. The control logic unit is further configured to determine the temperature of each of the remote temperature sensors based on this correlation, and also configured to determine the maximum temperature of all of the temperature sensors.

Abstract: The gate and active regions of a device are formed and alternating steps of applying and removing nitride and oxide layers allows exposing silicon in different areas while keeping silicon or polysilicon in other area covered with nitride. Metal layers are deposited over the exposed silicon or polysilicon and annealing forms a silicide layer in the selected exposed areas. The oxide and/or nitride layers are removed from the covered areas and another metal layer is deposited. The anneal process is repeated with silicide of one thickness formed over the second exposed areas with additional thickness of silicide formed over the previous silicide thickness.

Abstract: Embodiments of the video data capture and stream method comprise intercepting a flip function call comprising a call by the video application to flip frames between a display and a buffer, grabbing a copy of the current frame that would normally be processed by a central processing unit (CPU), placing the copy in a queue for processing by a graphics processing unit (GPU), wherein processing by the GPU is significantly faster than processing by the CPU.

Abstract: A method and system for handling a security exception. The method includes creating a security exception stack frame in secure memory at a base address. The method also includes writing a faulting code sequence address and one or more register values into the security exception stack frame, and executing a plurality of security exception instructions.

Abstract: According to one exemplary embodiment, a method includes a step of forming a polysilicon layer over a substrate by using a deposition process, where the deposition process causes polysilicon nodule defects to form on a top surface of the polysilicon layer. The method further includes performing a polysilicon CMP process on the polysilicon layer, where the polysilicon CMP process removes a substantial percentage of the polysilicon nodule defects from the top surface of the polysilicon layer. The CMP process removes at least 95.0 percent of the polysilicon nodule defects from the top surface of the polysilicon layer. According to this embodiment, the polysilicon CMP process utilizes a polishing pressure that is less than 1.5 psi. The polysilicon CMP process also utilizes a table speed of between 20.0 rpm and 40.0 rpm. The polysilicon CMP process further utilizes a colloidal silica slurry.

Abstract: The present invention provides an integrated circuit design system, comprising providing a design system in a computer system, providing a layout design tool coupled to the design system, wherein the layout design tool creates an interconnect structure to satisfy electromigration criteria, and manipulating a design database within the design system.

Abstract: A method and apparatus for guaranteeing clock edge synchronization is disclosed. In one embodiment, a system for synchronizing clock signals includes a clock unit and a synchronization unit. Both the clock unit and the synchronization unit may be configured to receive a reference clock signal. The clock unit may be configured to drive a plurality of domain clock signals to various clock domains. The synchronization unit may be configured to assert a synchronization pulse once every N reference clock cycles. Clock edges of the domain clock signals may be aligned with each other responsive to asserting the synchronization pulse.

Abstract: The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate compensating for retrograde feature profiles on an imprint mask. An aspect of the invention generates feedback information that facilitates control of imprint mask feature profile via employing a scatterometry system to detect retrograde feature profiles, and mitigating the retrograde profiles via a spacer etchback procedure.

Abstract: A microelectronic structure and a method for fabricating the microelectronic structure use a dielectric layer that is located and formed upon a first conductor layer. An aperture is located through the dielectric layer. The aperture penetrates vertically into the first conductor layer and extends laterally within the first conductor layer beneath the dielectric layer while not reaching the dielectric layer, to form an extended and winged aperture. A contiguous via and interconnect may be formed anchored into the extended and winged aperture while using a plating method, absent voids.

Abstract: The present invention provides a method and apparatus for dynamic adjustment of a sampling plan. The method includes accessing wafer electrical test data associated with at least one workpiece that has been processed by at least one processing tool. The method also includes determining, based on the wafer electrical test data, at least one sampling plan for at least one measurement device configured to measure at least one parameter associated with workpieces processed by the at least one processing tool.

Abstract: Disclosed are methods and systems for granting an application-specific integrated circuit (ASIC) in a multi-ASIC environment controlled access to a shared resource. A system includes a first ASIC, a second ASIC, and a shared memory that stores a shared resource and a data set partitioned into fields. The first ASIC writes data to a first subset of the fields and reads data from the fields. The first ASIC includes first logic that computes a first value based on the data read from the fields. The second ASIC writes data to a second subset of the fields and reads data from the fields. The second ASIC includes second logic that computes a second value based on the data read from the fields. Based on the first and second values respectively computed by the first and second logic, only one of the first and second ASICs gains access to the shared resource.

Abstract: A method for scheduling preventative maintenance tasks includes defining a set of global time periods. Members of a set of preventative maintenance tasks associated with a plurality of machines for are scheduled execution during the global time periods based on capacities of the machines and production targets for the machines. A plurality of time slots is defined for a selected global period having a selected preventative maintenance task scheduled for execution therein. A selected time slot from the plurality of time slots is scheduled for performing the selected preventative maintenance task based on work in process levels for with the associated machine over the time slots.