Patents Assigned to Advanced Micro Devices
  • Doped structure for finfet devices
    Patent number: 7416925
    Abstract: A semiconductor device includes a substrate and an insulating layer on the substrate. The semiconductor device also includes a fin structure formed on the insulating layer, where the fin structure includes first and second side surfaces, a dielectric layer formed on the first and second side surfaces of the fin structure, a first gate electrode formed adjacent the dielectric layer on the first side surface of the fin structure, a second gate electrode formed adjacent the dielectric layer on the second side surface of the fin structure, and a doped structure formed on an upper surface of the fin structure in the channel region of the semiconductor device.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: August 26, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ming-Ren Lin, Bin Yu
  • Method and system for modeling a stream of products in a manufacturing environment by process and tool categorization
    Patent number: 7415316
    Abstract: By estimating the processing rate on the basis of capacity factors, which are classified with respect to process recipes, i.e., technology nodes, and process tool groups, a fast response to various conditions may be accomplished, thereby providing significantly enhanced flexibility in estimating the productivity and rentability of a manufacturing environment.
    Type: Grant
    Filed: October 17, 2006
    Date of Patent: August 19, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Thomas Quarg
  • SOI Device with charging protection and methods of making same
    Patent number: 7414289
    Abstract: The present invention is directed to an SOI device with charging protection and methods of making the same. In one illustrative embodiment, a device is formed on an SOI substrate including a bulk substrate, a buried insulation layer and an active layer. The device includes a transistor formed in an isolated portion of the active layer, the transistor including a gate electrode and a source region. The device further includes a first conductive bulk substrate contact extending through the active layer and the buried insulation layer, the first conductive bulk substrate contact being conductively coupled to the source region and the bulk substrate, and a second conductive bulk substrate contact extending through the active layer and the buried insulation layer, the second conductive bulk substrate being conductively coupled to the gate electrode and the bulk substrate.
    Type: Grant
    Filed: July 17, 2006
    Date of Patent: August 19, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David D. Wu, Jingrong Zhou
  • Processor with dependence mechanism to predict whether a load is dependent on older store
    Patent number: 7415597
    Abstract: A processor may include a scheduler configured to issue operations and a load store unit configured to execute memory operations issued by the scheduler. The load store unit is configured to store information identifying memory operations issued to the load store unit. In response to detection of incorrect data speculation for one of the issued memory operations, the load store unit is configured to replay at least one of the issued memory operations by providing an indication to the scheduler. The scheduler is configured to responsively reissue the memory operations identified by the load store unit.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: August 19, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael A. Filippo, James K. Pickett
  • Method for forming a self-aligned nitrogen-containing copper silicide capping layer in a microstructure device
    Patent number: 7413985
    Abstract: By forming a copper/silicon/nitrogen alloy in a surface portion of a copper-containing region on the basis of a precursor layer, highly controllable and reliable process conditions may be established. The precursor layer may be formed on the basis of a liquid precursor solution, which may exhibit a substantially self-aligned and self-limiting deposition behavior.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: August 19, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christof Streck, Volker Kahlert
  • Stressed MOS device and method for its fabrication
    Patent number: 7410859
    Abstract: A stressed MOS device and a method for its fabrication are provided. The MOS device comprises a substrate having a surface, the substrate comprising a monocrystalline semiconductor material having a first lattice constant. A channel region is formed of the monocrystalline silicon material adjacent the surface. A stress inducing monocrystalline semiconductor material having a second lattice constant greater than the first lattice constant is grown under the channel region to exert a horizontal tensile stress on the channel region.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: August 12, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Igor Peidous, Linda R. Black, Frank Wirbeleit
  • Method and apparatus for out of order writing of status fields for receive IPsec processing
    Patent number: 7412726
    Abstract: Network interface systems are disclosed comprising a bus interface system, a media access control system, a memory system, a security system for selectively encrypting outgoing data and decrypting incoming data, where the network interface system may be fabricated as a single integrated circuit chip. Systems and methods are disclosed wherein out-of-order writing is used to improve throughput for the security system on the receive end.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: August 12, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Somnath Viswanath
  • Method and apparatus for using low power training
    Patent number: 7411998
    Abstract: A method and apparatus are provided. The method includes establishing a communication channel between a first transceiver and a second transceiver in low power mode, and determining a training parameter using the communication channel. The method also includes performing training in response to determining the training parameter. The apparatus, capable of communicating with a transceiver, includes a first and second logic. The first logic is capable of establishing a communication channel with the transceiver in a low power mode. The second logic is capable determining a training parameter using the communication channel, and providing the training parameter to the transceiver.
    Type: Grant
    Filed: January 20, 2000
    Date of Patent: August 12, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Terry L. Cole
  • Method of reducing contamination by removing an interlayer dielectric from the substrate edge
    Patent number: 7410885
    Abstract: By performing at least one additional wet chemical etch process in the edge region and in particular on the bevel of a substrate during the formation of a metallization layer, the dielectric material, especially the low-k dielectric material, may be reliably removed from the bevel prior to the formation of any barrier and metal layers. Moreover, an additional wet chemical etch process may be performed after the deposition of the metal to remove any unwanted metal and barrier material from the edge region and the bevel. Accordingly, defect issues and contamination of substrates and process tools may be efficiently reduced.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: August 12, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Holger Schuehrer, Christin Bartsch, Carsten Hartig
  • Semiconductor component having a contact structure and method of manufacture
    Patent number: 7407882
    Abstract: A semiconductor component having a titanium silicide contact structure and a method for manufacturing the semiconductor component. A layer of dielectric material is formed over a semiconductor substrate. An opening having sidewalls is formed in the dielectric layer and exposes a portion of the semiconductor substrate. Titanium silicide is disposed on the dielectric layer, sidewalls, and the exposed portion of the semiconductor substrate. The titanium silicide may be formed by disposing titanium on the dielectric layer, sidewalls, and exposed portion of the semiconductor substrate and reacting the titanium with silane. Alternatively, the titanium silicide may be sputter deposited. A layer of titanium nitride is formed on the titanium silicide. A layer of tungsten is formed on the titanium nitride. The tungsten, titanium nitride, and titanium silicide are polished to form the contact structures.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: August 5, 2008
    Assignees: Spansion LLC, Advanced Micro Devices, Inc.
    Inventors: Connie Pin-Chin Wang, Paul R. Besser, Wen Yu, Jinsong Yin, Keizaburo Yoshie
  • Combination of non-lithographic shrink techniques and trim process for gate formation and line-edge roughness reduction
    Patent number: 7405032
    Abstract: The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate the reduction of line-edge roughness (LER) during gate formation in an integrated circuit. Systems and methods are disclosed for improving critical dimension (CD) of photoresist lines, comprising a non-lithographic shrink component that facilitates mitigating LER, and a trim etch component that facilitates achieving and/or restoring a target critical dimension.
    Type: Grant
    Filed: August 21, 2003
    Date of Patent: July 29, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gilles Amblard, Srikanteswara Dakshina-Murthy, Bhanwar Singh
  • Low contact resistance CMOS circuits and methods for their fabrication
    Patent number: 7405112
    Abstract: A low contact resistance CMOS integrated circuit and method for its fabrication are provided. The CMOS integrated circuit comprises a first transition metal electrically coupled to the N-type circuit regions and a second transition metal different than the first transition metal electrically coupled to the P-type circuit regions. A conductive barrier layer overlies each of the first transition metal and the second transition metal and a plug metal overlies the conductive barrier layer.
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: July 29, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Paul R. Besser
  • Method and system for self-assembling instruction opcodes for a custom random functional test of a microprocessor
    Patent number: 7404110
    Abstract: In one embodiment, a method may include generating a test code segment including a number of selected opcodes and executing the test code segment for a plurality of iterations. The method may also include saving a first test result of the execution of the test code segment after a first iteration and comparing additional test results of each subsequent iteration with the first test result. The method may further include determining whether any of the additional test results are different than the first test result.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: July 22, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Trent W. Johnson
  • Method and system for advanced process control including tool dependent machine constants
    Patent number: 7403832
    Abstract: A controller and a method of controlling a process tool is provided, in which machine constants used for calibrating manipulated variables of the control algorithm are explicitly introduced into the process model, thereby providing an enhanced controller behavior immediately after the introduction of new measurement values of the machine constants.
    Type: Grant
    Filed: April 18, 2006
    Date of Patent: July 22, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Uwe Schulze, Uwe Knappe
  • Method of forming a semiconductor device
    Patent number: 7402485
    Abstract: A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer structure from a subsequent cleaning process. An epitaxial layer is formed subsequent to the cleaning process.
    Type: Grant
    Filed: September 19, 2005
    Date of Patent: July 22, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: William G. En, Thorsten Kammler, Eric N. Paton, Scott D. Luning
  • Single electron devices formed by laser thermal annealing
    Patent number: 7402505
    Abstract: A semiconductor device with a superlattice and method of making same includes forming a layer of amorphous silicon over a substrate, and forming a layer of nanocrystals by laser thermal annealing the layer of amorphous silicon. A gate dielectric is formed between the layer of amorphous silicon and the substrate. A dielectric layer is formed on the layer of amorphous silicon. The steps of forming the layer of amorphous silicon and forming the dielectric layer can be repeated. The thickness of the dielectric layer is between about 25 to 40 angstroms, and the thickness of the amorphous silicon layer is between about 30 to 50 angstroms. The average diameter of the nanocrystals is less than 40 angstroms.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: July 22, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Zoran Krivokapic
  • Method and apparatus for controlling the thickness of a selective epitaxial growth layer
    Patent number: 7402207
    Abstract: Methods and systems for permitting thickness control of the selective epitaxial growth (SEG) layer in a semiconductor manufacturing process, for example raised source/drain applications in CMOS technologies, are presented. These methods and systems provide the capability to measure the thickness of an SEG film in-situ utilizing optical ellipsometry equipment during or after SEG layer growth, prior to removing the wafer from the SEG growth tool. Optical ellipsometry equipment can be integrated into the SEG platform and control software, thus providing automated process control (APC) capability for SEG thickness. The integration of the ellipsometry equipment may be varied, dependent upon the needs of the fabrication facility, e.g., integration to provide ellipsometer monitoring of a single process tool, or multiple tool monitoring, among other configurations.
    Type: Grant
    Filed: May 5, 2004
    Date of Patent: July 22, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Paul R. Besser, Eric N. Paton, William G. En
  • Transistor device having an increased threshold stability without drive current degradation
    Patent number: 7402497
    Abstract: By removing a portion of a halo region or by avoiding the formation of the halo region within the extension region, which may be subsequently formed on the basis of a re-grown semiconductor material, the threshold roll off behavior may be significantly improved, wherein an enhanced current drive capability may simultaneously be achieved.
    Type: Grant
    Filed: October 20, 2006
    Date of Patent: July 22, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andy Wei, Thorsten Kammler, Jan Hoentschel, Manfred Horstmann
  • Plasma state monitoring to control etching processes and across-wafer uniformity, and system for performing same
    Patent number: 7402257
    Abstract: The present invention is generally directed to plasma state monitoring to control etching processes and across-wafer uniformity, and a system for performing same. In one illustrative embodiment, the method comprises generating a plasma within an etching tool, monitoring at least one characteristic of the generated plasma, and controlling at least one parameter of a plasma etching process performed in the tool based upon the monitored at least one characteristic of the plasma. In another illustrative embodiment, the method comprises generating a plasma within an etch tool, performing a plasma etching process within the etch tool, determining at least one characteristic of the plasma, and controlling at least one parameter of the etching process based upon a comparison of the determined at least one characteristic of the plasma and a target value for the determined at least one characteristic of the plasma.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: July 22, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thomas J. Sonderman, Richard J. Markle
  • Method of controlling access to control registers of a microprocessor
    Patent number: 7401358
    Abstract: A method of controlling access to a control register of a microprocessor. The method of controlling access to a control register of a processor having a normal execution mode and a secure execution mode may include storing state and mode information in the control register, allowing a software invoked write access to modify the state and mode information within the control register during the normal execution mode and selectively inhibiting the software invoked write access during the secure execution mode.
    Type: Grant
    Filed: April 18, 2003
    Date of Patent: July 15, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David S. Christie, Kevin J. McGrath