Patents Assigned to Advanced Micro Devices
  • Embedded strain layer in thin SOI transistors and a method of forming the same
    Patent number: 7399663
    Abstract: By forming a deep recess through the buried insulating layer and re-growing a strained semiconductor material, an enhanced strain generation mechanism may be provided in SOI-like transistors. Consequently, the strain may also be efficiently created by the embedded strained semiconductor material across the entire active layer, thereby significantly enhancing the performance of transistor devices, in which two channel regions may be defined.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: July 15, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jan Hoentschel, Andy Wei, Manfred Horstmann, Thorsten Kammler
  • Electric-hydraulic power unit
    Patent number: 7398830
    Abstract: The present invention is directed to an electric-hydraulic power unit. In one illustrative embodiment, the power unit comprises a body having a movable pressure barrier positioned therein, the movable pressure barrier defining first and second chambers therein, a configurable flow path in fluid communication with the first and second chambers, and at least one valve for configuring the flow path in a first state wherein fluid may flow within the flow path only in a direction from the first chamber toward the second chamber, and a second state wherein fluid within the flow path may flow in both directions between the first and second chambers.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: July 15, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John A. Johansen, Vidar Sten Halvorsen, Michael R. Williams
  • Integrated circuit design with cell-based macros
    Patent number: 7401310
    Abstract: A method for designing integrated circuits may include custom designing, at the transistor level, individual cells to be incorporated into cell-based macros. A macro-level function of an integrated circuit's design specification requiring custom, transistor-level design may be identified and custom cells may be designed at the transistor-level to meet the design specification. Custom designed cells may be included in cell-based macros, thus allowing cell-based simulation and verification methodologies and tools to be used on the integrated circuit design. Static timing analysis, circuit extraction and other characteristics may be defined for each custom cell and the timing analysis and circuit extraction for cell-based macros may be defined based on the timing and extraction information for the custom cells included in the macro.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: July 15, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Robert C. Thaden, Steven C. Hesley, Christopher B. Ang, Jeffery E. Short, Eric W. Mahurin
  • Technique for creating different mechanical strain in different channel regions by forming an etch stop layer stack having differently modified intrinsic stress
    Patent number: 7396718
    Abstract: A technique is provided that allows the formation of contact etch stop layers having different intrinsic stress for different transistors, while substantially avoiding any device degradation owing to the partial removal of the contact etch stop layer. Hereby, an additional thin etch stop layer is provided prior to the formation of the contact etch stop layers, thereby substantially maintaining the integrity of metal silicide regions, when a portion of an initially deposited contact etch stop layer is removed.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: July 8, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kai Frohberg, Matthias Schaller, Joerg Hohage, Holger Schuehrer
  • Programmable interleaving in multiple-bank memories
    Patent number: 7398362
    Abstract: A method includes receiving a linear address for accessing a multiple-bank memory, determining a first bit location of the linear address based on a first register value, and providing a bank identifier based on a value at the first bit location of the linear address. Another method includes receiving, at a memory controller coupled to a multiple-bank memory, input indicating a mapping of values at identified bit locations of a linear address to corresponding values of a memory address output. The memory address output includes a bank identifier based on a value at one or more of at least three bit locations of the linear address and a value of the input is programmable.
    Type: Grant
    Filed: December 9, 2005
    Date of Patent: July 8, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Brett A. Tischler
  • Method and apparatus for characterizing arrays using cell-based timing elements
    Patent number: 7398495
    Abstract: The present invention provides a method and apparatus for characterizing a memory array. The method includes accessing information indicative of a transistor-level circuit design of a column of a memory array and determining at least one component of a cell representative of the column of the memory array based on the information indicative of the transistor-level circuit design and at least one timing rule for at least one signal associated with the column of the memory array. The method also includes determining at least one time delay associated with the cell based on the at least one component of at least one cell.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: July 8, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Russell Schreiber, David M. Newmark, Joe Spector
  • Fast add rotate add operation
    Patent number: 7395306
    Abstract: A system and associated methodology for performing a fast add rotate add operation is disclosed. Two separate addition functions conventionally separated by a shift operation are performed as a single operation thereby reducing the number of acts and resources required to perform the add rotate add operation.
    Type: Grant
    Filed: September 3, 2003
    Date of Patent: July 1, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Siaw-Kang Lai, Atul Garg
  • Integrated circuit with a hibernate mode and method therefor
    Patent number: 7395443
    Abstract: An integrated circuit (100) includes a firewall input terminal, a first circuit (110, 120, 170, 172), and a second circuit (220). The firewall input terminal is for receiving a firewall input signal. The first circuit (110, 120, 170, 172) is coupled to a first power supply voltage terminal (203) and has an output for providing a control signal. The second circuit is coupled to a second power supply voltage terminal (210), to the firewall input terminal (214), and to the first circuit (110, 120, 170, 172). When the firewall input signal is inactive, an activation of the control signal affects the operation of the second circuit. When the firewall input signal is active, an activation of the control signal does not affect the operation of the second circuit.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: July 1, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Stephen C. Kromer, James J. Montanaro, Richard T. Witek, Kathryn J. Hoover
  • Multi-layer printed circuit board comprising a through connection for high frequency applications
    Patent number: 7394027
    Abstract: A high frequency multi-layer printed circuit board, according to the present invention, comprises a through connection having an impedance adapting structure surrounding the through connection and enabling an adjustment of the characteristic impedance of the through connection to a desired value. Thus, high frequency signals may be led through the printed circuit board with reduced signal deformation. The high frequency multi-layer printed circuit board is applicable for high frequency signals up to the GHz-range.
    Type: Grant
    Filed: July 13, 2005
    Date of Patent: July 1, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Heiko Kaluzni, Andreas Huschka
  • LOW LATENCY CADENCE DETECTION FOR FRAME RATE CONVERSION
    Publication number: 20080151109
    Abstract: A frame rate converter sequentially buffers video frames in a sequence of video frames in a buffer and interpolates at least two of the plurality of video frames in the buffer based on at least one interpolation parameter, to form interpolated output frames. Conveniently, the interpolation parameter is adjusted with each newly buffered frame in dependence on the current value of the cadence of the frame sequence. In this way, delays associated with cadence detection may be reduced.
    Type: Application
    Filed: December 26, 2006
    Publication date: June 26, 2008
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Daniel Doswald
  • VIDEO PROCESSOR ARCHITECTURE AND METHOD FOR FRAME RATE CONVERSTION
    Publication number: 20080151108
    Abstract: A video processor, upstream of a frame rate converter determines video attribute data. This attribute data is formatted and passed along a channel to the frame rate converter. The frame rate converter extracts the attribute data from the channel for use in frame rate conversion. The frame rate converter may thus rely on attribute data obtained by the video processor, and need not re-analyze video frames.
    Type: Application
    Filed: December 26, 2006
    Publication date: June 26, 2008
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Daniel Doswald
  • MEMORY DEVICE ETCH METHODS
    Publication number: 20080153298
    Abstract: A method of manufacturing a memory device forms a first dielectric layer over a substrate, forms a charge storage layer over the first dielectric layer, forms a second dielectric layer over the charge storage layer, and forms a control gate layer over the second dielectric layer. The method also forms a hard mask layer over the control gate layer, forms a bottom anti-reflective coating (BARC) layer over the hard mask layer, and provides an etch chemistry that includes tetrafluoromethane (CF4) and trifluoromethane (CHF3) to etch at least the control gate layer.
    Type: Application
    Filed: December 26, 2006
    Publication date: June 26, 2008
    Applicants: Advanced Micro Devices, Inc., Spansion LLC
    Inventors: Angela T. Hui, Jihwan Choi
  • Derived metric for monitoring die placement
    Patent number: 7390681
    Abstract: A method for monitoring die placement includes receiving measurements of an alignment of a semiconductor die mounted in a package by a die packaging tool. The measurements include center offset metrics associated with displacement of a center of the die. A plurality of corner offset metrics is determined based on the center offset metrics and dimensions of the die. A maximum one of the corner offset metrics is selected as a die placement metric. An out of tolerance condition with the die packaging tool is identified based on the die placement metric.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: June 24, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventor: John E. Tristan
  • Contact resistance test structure and methods of using same
    Patent number: 7391226
    Abstract: The present invention is directed to a contact resistance test structure and methods of using same. In one illustrative embodiment, the method includes forming a test structure comprised of two gate electrode structures, forming a plurality of conductive contacts to a doped region between the two gate electrode structures, forcing a current through the test structure and determining a resistance of at least one of the conductive contacts based upon, in part, the forced current.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: June 24, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark W. Michael, Raymond G. Stephany
  • INTEGRATED CIRCUIT SYSTEM WITH IMPLANT OXIDE
    Publication number: 20080142874
    Abstract: A method for forming an integrated circuit system is provided including forming a substrate; forming a stack over the substrate, the stack having a sidewall and formed from a charge trap layer and a semi-conducting layer; and slot plane antenna oxidizing the stack for forming a protection enclosure having a protection layer along the sidewall.
    Type: Application
    Filed: December 16, 2006
    Publication date: June 19, 2008
    Applicants: Spansion LLC, Advanced Micro Devices, Inc.
    Inventors: Shenqing Fang, Rinji Sugino, Jayendra Bhakta, Takashi Orimoto, Hiroyuki Nansei, Yukio Hayakawa, Hidehiko Shiraiwa, Takayuki Maruyama, Kuo-Tung Chang, YouSeok Suh, Amol Ramesh Joshi, Harpreet Sachar, Simon Siu-Sing Chan
  • Device and method of data transfer
    Publication number: 20080147914
    Abstract: Data transfer between different clock domains occurs through a FIFO. The relative number of read and write FIFO access cycles to the FIFO is controlled to maintain a desired latency.
    Type: Application
    Filed: September 28, 2006
    Publication date: June 19, 2008
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Wade L. Williams, Philip E. Madrid
  • Design Rules Checking Augmented With Pattern Matching
    Publication number: 20080148211
    Abstract: Layout patterns are identified as problematic when they have particular parameters required to exceed standard limits. The problematic layout patterns are associated with preferred design rules in a DRC-Plus deck. Layout data is scanned to generate match locations of any problematic layout patterns. The match locations are forwarded to a DRC engine that compares layout parameters of the match locations to corresponding preferred layout rules in the DRC-Plus deck. The DRC-Plus check results are used to modify the layout to improve manufacturability of the layout.
    Type: Application
    Filed: December 19, 2006
    Publication date: June 19, 2008
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Vito Dai, Jie Yang, Norma Rodriguez, Luigi Capodieci
  • Sensing device for floating body cell memory and method thereof
    Publication number: 20080144367
    Abstract: A memory device includes a memory array and a sense amplifier. The memory array includes a floating body cell configured to store a bit value. The sense amplifier includes a bit output configured to provide an output voltage representative of the bit value and a reference source configured to provide a reference voltage. The sense amplifier further includes a current mirror configured to provide a current to the first floating body cell based on the reference voltage, and a differential amplifier circuit configured to determine the output voltage based on the reference voltage and a voltage across the floating body cell resulting from application of the current to the floating body cell.
    Type: Application
    Filed: December 15, 2006
    Publication date: June 19, 2008
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Michael A. Dreesen, John J. Wuu, Donald R. Weiss
  • Microprocessor including a configurable translation lookaside buffer
    Patent number: 7389402
    Abstract: A translation lookaside buffer may include control functionality coupled to a first storage and a second storage. The first storage includes a first plurality of entries for storing address translations corresponding to a plurality of page sizes. The second storage includes a second plurality of entries for storing address translations corresponding to the plurality of page sizes. In response to receiving a first address translation associated with a first page size, the control functionality may allocate the first plurality of entries to store address translations corresponding to the first page size. In addition, in response to receiving a request including an address that matches an address translation stored within the first storage, the control functionality may copy a matching address translation from the first storage to the second storage.
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: June 17, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gerald D. Zuraski, Jr., Swamy Punyamurtula
  • Post fabrication CD modification on imprint lithography mask
    Patent number: 7386162
    Abstract: The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate compensating for imprint mask critical dimension error(s). An aspect of the invention generates feedback information that facilitates control of imprint mask critical dimension via employing a scatterometry system to detect imprint mask critical dimension error, and mitigating the error via a spacer etchback procedure.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: June 10, 2008
    Assignee: Advanced Micro Devices, Inc
    Inventors: Srikanteswara Dakshina-Murthy, Bhanwar Singh, Ramkumar Subramanian