Patents Assigned to Advanced Semiconductor Engineering
  • Publication number: 20220201754
    Abstract: An electronic device, a transmission system, and a transmission method are provided. The electronic device includes a capturing module, a processing module, and a transmission module. The capturing module is configured to receive a first set of signals. The processing module is configured to select a second set of signals from the first set of signals based on a condition. The transmission module is configured to transmit the second set of signals.
    Type: Application
    Filed: December 18, 2020
    Publication date: June 23, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ting-Han CHEN, Yu-Chuang HSU, Alex Chi-Hong CHAN
  • Publication number: 20220189887
    Abstract: A capacitor structure includes a first metal layer, a first metal oxide layer, a second metal oxide layer, a first conductive member, a second conductive member and a metal composite structure. The first metal layer has a first surface and a second surface opposite the first surface. The first metal oxide layer is formed on the first surface of the first metal layer. The second metal oxide layer is formed on the second surface of the first metal layer. The first conductive member penetrates through the capacitor structure and is electrically isolated from the first metal layer. The second conductive member is electrically connected to the first metal layer. The metal composite structure is disposed between the second conductive member and the first metal layer.
    Type: Application
    Filed: March 1, 2022
    Publication date: June 16, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen Hung HUANG
  • Publication number: 20220187068
    Abstract: An optical module includes: a carrier; an optical element disposed on the upper side of the carrier; and a housing disposed on the upper side of the carrier, the housing defining an aperture exposing at least a portion of the optical element, an outer sidewall of the housing including at least one singulation portion disposed on the upper side of the carrier, wherein the singulation portion of the housing is a first portion of the housing, and wherein the housing further includes a second portion and a surface of the singulation portion of the housing is rougher than a surface of the second portion of the housing.
    Type: Application
    Filed: March 1, 2022
    Publication date: June 16, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ying-Chung CHEN, Hsun-Wei CHAN, Lu-Ming LAI, Kuang-Hsiung CHEN
  • Publication number: 20220181267
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes an electronic component, a conductive contact, and a first shielding layer. The electronic component has a first surface, a lateral surface angled with the first surface, and a second surface opposite to the first surface. The conductive contact is connected to the first surface of the electronic component. The first shielding layer is disposed on the lateral surface of the electronic component and a portion of the first surface of the electronic component. The first shielding layer contacts the conductive contact.
    Type: Application
    Filed: December 3, 2020
    Publication date: June 9, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Yuan KUNG, Meng-Wei HSIEH
  • Publication number: 20220181268
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a device package and a shielding layer. The device package includes an electronic device unit and has a first surface, a second surface opposite to the first surface, and a third surface connecting the first surface to the second surface. The shielding layer is disposed on the first surface and the second surface of the device package. A common edge of the second surface and the third surface includes a first portion exposed from the shielding layer by a first length, and a common edge of the first surface and the third surface includes a second portion exposed from the shielding layer by a second length that is different from the first length.
    Type: Application
    Filed: December 3, 2020
    Publication date: June 9, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Yuan KUNG, Hung-Yi LIN, Meng-Wei HSIEH, Yu-Pin TSAI
  • Publication number: 20220181235
    Abstract: The subject application discloses a substrate. The substrate includes a first conductive layer, a first bonding layer, a first dielectric layer, and a conductive via. The first bonding layer is disposed on the first conductive layer. The first dielectric layer is disposed on the first bonding layer. The conductive via penetrates the first dielectric layer and is electrically connected with the first conductive layer.
    Type: Application
    Filed: December 3, 2020
    Publication date: June 9, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen Hung HUANG
  • Publication number: 20220181264
    Abstract: An electronic device package includes a substrate, a first semiconductor die, a second semiconductor die and an encapsulant. The substrate includes a first surface, and a second surface opposite to the first surface. The substrate defines a cavity recessed from the first surface. The first semiconductor die is disposed in the cavity. The second semiconductor die is disposed over and electrically connected to the first semiconductor die. The encapsulant is disposed in the cavity of the substrate. The encapsulant encapsulates a first sidewall of the first semiconductor die, and exposes a second sidewall of the first semiconductor die.
    Type: Application
    Filed: February 22, 2022
    Publication date: June 9, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Mei-Ju LU, Jr-Wei LIN
  • Publication number: 20220181277
    Abstract: The present disclosure provides a semiconductor a semiconductor device package includes a substrate, an electronic component disposed on the substrate, a package body disposed on the substrate and encapsulating the electronic component, and a capacitor disposed above the electronic component. The capacitor is exposed from the package body.
    Type: Application
    Filed: December 4, 2020
    Publication date: June 9, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Wei HSIEH, Ming-Tau HUANG, Yu-Chih LEE
  • Publication number: 20220181182
    Abstract: The present disclosure relates to an electronic component. The electronic component includes a first surface, a first functional region, and a non-functional region. The first functional region is disposed on the first surface of the electronic component. The non-functional region is recessed from the first surface of the electronic component.
    Type: Application
    Filed: December 3, 2020
    Publication date: June 9, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jenchun CHEN, Kuo Kai HUANG
  • Publication number: 20220165683
    Abstract: An assembly structure and a method for manufacturing the same are provided. The method for manufacturing the assembly structure includes providing a substrate defining an active region and a side rail surrounding the active region; and forming a frame structure on the side rail.
    Type: Application
    Filed: November 25, 2020
    Publication date: May 26, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Yu-Ju LIAO
  • Publication number: 20220165682
    Abstract: A semiconductor package structure includes a semiconductor package structure includes a first supporting bar, a second supporting bar and an encapsulant. The second supporting bar is adjacent to the first supporting bar. The first supporting bar and the second supporting bar extend substantially along a first direction. The encapsulant covers the first supporting bar and the second supporting bar. The encapsulant defines a first recess and a second recess recessed from a lower surface of the encapsulant. The first recess extends substantially along a second direction different from the first direction. The second recess is located between the first recess and the second supporting bar.
    Type: Application
    Filed: November 20, 2020
    Publication date: May 26, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hui-Yu LEE, Hui-Chen HSU
  • Publication number: 20220157745
    Abstract: The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate, and the electronic component includes a magnetic layer and a conductive wire. The conductive wire includes a first section embedded in the magnetic layer, and a second section connected to the first section and thinner than the first section. A first upper surface of the first section is covered by the magnetic layer, a second upper surface of the second section is lower than the first upper surface, and the magnetic layer includes a first recess disposed in the upper surface and exposing the second upper surface of the second section. The first conductive trace is in the first recess and electrically connected to the second upper surface of the second section of the conductive wire.
    Type: Application
    Filed: January 31, 2022
    Publication date: May 19, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wu Chou HSU, Chih-Cheng LEE, Min-Yao CHEN, Hsing Kuo TIEN
  • Publication number: 20220157742
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The package structure includes an outer lead portion, an inner lead portion, an encapsulant, and a first conductive layer. The outer lead portion has a first surface and a second surface opposite to the first surface. The inner lead portion is connected to the outer lead portion. The inner lead portion has a first surface and a second surface opposite to the first surface. The encapsulant covers the first surface of the outer lead portion and the first surface of the inner lead portion. The second surface of the outer lead portion and the second surface of the inner lead portion are substantially coplanar and are recessed from a surface of the encapsulant. The first conductive layer is disposed on the second surface of the outer lead portion.
    Type: Application
    Filed: November 19, 2020
    Publication date: May 19, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Yu-Ying LEE
  • Publication number: 20220157746
    Abstract: The present disclosure provides an antenna module. The antenna module includes a first layer, a second layer, a first antenna, and a second antenna. The first layer has a first dielectric constant. The second layer is adjacent to the first layer. The second layer has a second Dk lower than the first Dk. The first antenna is disposed on the first layer and is configured for operating at a first frequency. The second antenna is disposed on the second layer and is configured for operating at a second frequency higher than the first frequency.
    Type: Application
    Filed: November 19, 2020
    Publication date: May 19, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Yu HO, Meng-Wei HSIEH
  • Publication number: 20220157709
    Abstract: A semiconductor package structure and method for manufacturing the same are provided. The semiconductor package structure includes a first electronic component, a conductive pillar, a second electronic component, and a conductive through via. The conductive pillar is disposed on the first electronic component and has a first surface facing away from the first electronic component. The second electronic component is disposed on the first electronic component. The conductive through via extends through the second electronic component and has a first surface facing away from the first electronic component. The first surface of the conductive through via and the first surface of the conductive pillar are substantially coplanar.
    Type: Application
    Filed: November 18, 2020
    Publication date: May 19, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Chiang Shih, Meng-Wei Hsieh, Hung-Yi Lin, Cheng-Yuan Kung
  • Publication number: 20220157775
    Abstract: A package structure includes: 1) a circuit substrate; 2) a first semiconductor device disposed on the circuit substrate; 3) a first insulation layer covering a sidewall of the first semiconductor device; 4) a second insulation layer covering the first insulation layer; and 5) a third insulation layer disposed on the circuit substrate and in contact with the second insulation layer.
    Type: Application
    Filed: January 11, 2022
    Publication date: May 19, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chi-Chih SHEN, Jen-Chuan CHEN, Tommy PAN
  • Publication number: 20220148936
    Abstract: A package structure and a circuit layer structure are provided in the present disclosure. The package structure includes a wiring structure, a first electronic device, a second electronic device and at least one dummy trace. The wiring structure includes a plurality of interconnection traces. The first electronic device and the second electronic device are disposed on the wiring structure, and electrically connected to each other through the interconnection traces. The dummy trace is adjacent to the interconnection traces. A mechanical strength of the at least one dummy trace is less than a mechanical strength of one of the interconnection traces.
    Type: Application
    Filed: November 6, 2020
    Publication date: May 12, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen-Long LU
  • Publication number: 20220148989
    Abstract: A semiconductor package includes a first substrate, a first flow channel and a second flow channel. The first flow channel is on the first substrate. The second flow channel is on the first substrate and in fluid communication with the first flow channel. The second flow channel is spaced from an inlet and an outlet of the first flow channel. The first flow channel and the second flow channel constitute a bonding region of the first substrate.
    Type: Application
    Filed: November 6, 2020
    Publication date: May 12, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yung-Sheng LIN, Yun-Ching HUNG, An-Hsuan HSU, Chung-Hung LAI
  • Publication number: 20220148974
    Abstract: An assembly structure includes a core-computing section and a sub-computing section. The core-computing section has a first surface and a second surface opposite to the first surface. The core-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The sub-computing section has a first surface stacked on the first surface of the core-computing section and a second surface opposite to the first surface. The sub-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The assembly structure includes a first signal transmission path and a second signal transmission path. The first signal transmission path is between the at least one conductive via of the sub-computing section and the at least one conductive via of the core-computing section.
    Type: Application
    Filed: January 25, 2022
    Publication date: May 12, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Yuan KUNG, Hung-Yi LIN
  • Publication number: 20220148954
    Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes a conductive structure, an intermediate structure and a seed layer. The conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The conductive structure defines an accommodating hole. The intermediate structure is bonded to an inner surface of the accommodating hole. The seed layer is bonded to the accommodating hole through the intermediate structure.
    Type: Application
    Filed: November 6, 2020
    Publication date: May 12, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen Hung HUANG