Patents Assigned to Advanced Semiconductor Engineering
  • Publication number: 20200020827
    Abstract: An optical device includes a substrate, an electronic component, a lid and a barrier. The electronic component is disposed on the substrate. The electronic component has an active surface faces away from the substrate. The lid is disposed on the substrate. The lid has a wall structure extending toward the active surface of electronic component and is spaced apart from the active surface of the electronic component. The barrier is disposed on the active surface of the electronic component and is spaced apart from the wall structure of the lid.
    Type: Application
    Filed: July 8, 2019
    Publication date: January 16, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsin-Ying HO, Ying-Chung CHEN, Lu-Ming LAI
  • Publication number: 20200006315
    Abstract: A substrate structure includes at least one detachable first substrate unit and a substrate body. The detachable first substrate unit includes a plurality of corners and a plurality of first engagement portions. Each of the first engagement portions is disposed at each of the corners of the detachable first substrate unit. The substrate body includes a plurality of second substrate units, at least one opening and a plurality of second engagement portions. The opening is substantially defined by a plurality of sidewalls of the second substrate units, and includes a plurality of corners. Each of the second engagement portions is disposed at each of the corners of the opening. The detachable first substrate unit is disposed in the opening, and the second engagement portions are engaged with the first engagement portions.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 2, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Li-Chuan TSAI, Wu Chang WANG
  • Publication number: 20200002162
    Abstract: A semiconductor device package includes a semiconductor device, a non-semiconductor substrate over the semiconductor device, and a first connection element extending from the semiconductor device to the non-semiconductor substrate and electrically connecting the semiconductor device to the non-semiconductor substrate.
    Type: Application
    Filed: June 25, 2019
    Publication date: January 2, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chi Sheng TSENG, Lu-Ming LAI, Yu-Hsuan TSAI, Yin-Hao CHEN, Hsin Lin WU, San-Kuei YU
  • Publication number: 20200007086
    Abstract: The present disclosure relates to a power amplifier circuit. The power amplifier circuit includes a voltage-controlled current source and a current mirror. The voltage-controlled current source is configured to receive a first voltage and to generate a first current. The current mirror is connected to the voltage-controlled current source and to generate a second current in response to the first current. The second current continuously changes from 0 mA to about 120 mA as the first voltage continuously changes from 0 V to about 1 V.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Jaw-Ming DING
  • Publication number: 20190393297
    Abstract: A capacitor bank structure includes a plurality of capacitors, a protection material, a first dielectric layer and a plurality of first pillars. The capacitors are disposed side by side. Each of the capacitors has a first surface and a second surface opposite to the first surface, and includes a plurality of first electrodes and a plurality of second electrodes. The first electrodes are disposed adjacent to the first surface for external connection, and the second electrodes are disposed adjacent to the second surface for external connection. The protection material covers the capacitors, sidewalls of the first electrodes and sidewalls of the second electrodes, and has a first surface corresponding to the first surface of the capacitor and a second surface corresponding to the second surface of the capacitor. The first dielectric layer is disposed on the first surface of the protection material, and defines a plurality of openings to expose the first electrodes.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 26, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Yuan KUNG, Chien-Hua CHEN, Teck-Chong LEE, Hung-Yi LIN, Pao-Nan LEE, Hsin Hsiang WANG, Min-Tzu HSU, Po-Hao CHEN
  • Publication number: 20190393126
    Abstract: A semiconductor package device includes a substrate, an electronic component, and a thermal conductive layer. The electronic component is disposed on the substrate and includes a first surface facing away from the substrate. The thermal conductive layer is disposed above the first surface of the electronic component. The thermal conductive layer includes a plurality of portions spaced apart from each other.
    Type: Application
    Filed: January 30, 2019
    Publication date: December 26, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shiu-Fang YEN, Chang-Lin YEH, Jen-Chieh KAO
  • Publication number: 20190393140
    Abstract: A semiconductor device package includes a substrate, a first solder paste, an electrical contact and a first encapsulant. The substrate includes a conductive pad. The first solder paste is disposed on the pad. The electrical contact is disposed on the first solder paste. The first encapsulant encapsulates a portion of the electrical contact and exposes the surface of the electrical contact. The electrical contact has a surface facing away from the substrate. A melting point of the electrical contact is greater than that of the first solder paste. The first encapsulant includes a first surface facing toward the substrate and a second surface opposite to the first surface. The second surface of the first encapsulant is exposed to air.
    Type: Application
    Filed: February 5, 2019
    Publication date: December 26, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang-Lin YEH, Yu-Chang CHEN
  • Publication number: 20190393859
    Abstract: An electrical device includes an electronic component, a membrane and a cover. The electronic component has a first surface and a second surface opposite to the first surface. The electronic component has a cavity extending from the first surface of the electronic component into the electronic component. The membrane is disposed within the cavity of the electronic component. The cover is disposed on the first surface of the electronic component.
    Type: Application
    Filed: June 17, 2019
    Publication date: December 26, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Mark GERBER
  • Publication number: 20190385961
    Abstract: A semiconductor package device is provided that includes a first circuit layer having a first conductive layer and a first stud bump and a second circuit layer having a second conductive layer and a second stud bump. The first stud bump has a first portion and a second portion, and the second portion of the first stud bump is electrically connected to the second conductive layer. The second stud bump has a first portion and a second portion, and the second portion of the second stud bump is electrically connected to the first conductive layer. The first stud bump partially overlaps the second stud bump in a direction substantially perpendicular to the first circuit layer.
    Type: Application
    Filed: June 13, 2018
    Publication date: December 19, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen-Long LU
  • Publication number: 20190386187
    Abstract: An optical package device comprises a carrier, a die, a support element, and an encapsulant. The die is on the carrier. The support element is on the carrier and adjacent to the die. The encapsulant covers the die and the support element. The encapsulant has a first top surface over the die and a second top surface adjacent to the first top surface. A ratio of a distance between the first top surface and the second top surface of the encapsulant to a distance between the die and the first top surface of the encapsulant is less than 0.1.
    Type: Application
    Filed: June 18, 2018
    Publication date: December 19, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Mei-Yi WU, Ying-Chung CHEN, Hsin-Ying HO
  • Publication number: 20190378817
    Abstract: A semiconductor package device comprises a substrate, a first electronic component, a first encapsulant, a second electronic component, and a first conductive trace. The substrate has a first surface. The first electronic component is on the first surface of the substrate. The first encapsulant is on the first surface of the substrate and covers the first electronic component. The second electronic component is on the first encapsulant. The first conductive trace is within the first encapsulant. The first conductive trace is electrically connected to the second electronic component.
    Type: Application
    Filed: June 6, 2018
    Publication date: December 12, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jr-Wei LIN, Chia-Cheng LIU, Chien-Feng CHAN
  • Publication number: 20190378963
    Abstract: An electronic apparatus includes a substrate structure, a plurality of pillar bases, at least one light emitting device and a plurality of electrically connective materials. The substrate structure has a top surface and a bottom surface opposite to the top surface, and included a non III-V group material. The pillar bases are disposed adjacent to the top surface of the substrate structure. The light emitting device includes a III-V group material, and comprises a plurality of electrode pads. The electrically connective materials are interposed between the electrode pads of the light emitting device and the pillar bases.
    Type: Application
    Filed: June 3, 2019
    Publication date: December 12, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Te LIU, Chien Lin CHANG CHIEN, Chang Chi LEE
  • Publication number: 20190363039
    Abstract: A semiconductor package includes a base material, a capture land, an interconnection structure, a semiconductor chip and an encapsulant. The base material has a top surface and an inner lateral surface. The capture land is disposed in or on the base material, and has an outer side surface. The interconnection structure is disposed along the inner lateral surface of the base material, and on the capture land. The interconnection structure has an outer side surface. An outer side surface of the semiconductor package includes the outer side surface of the capture land and the outer side surface of the interconnection structure. The semiconductor chip is disposed on the top surface of the base material. The encapsulant is disposed adjacent to the top surface of the base material, and covers the semiconductor chip.
    Type: Application
    Filed: May 22, 2018
    Publication date: November 28, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Bernd Karl APPELT, You-Lung YEN, Kay Stefan ESSIG
  • Publication number: 20190363056
    Abstract: A substrate structure includes a substrate body, a bottom circuit layer, a first bottom protection structure and a second bottom protection structure. The substrate body has a top surface and a bottom surface opposite to the top surface. The bottom circuit layer is disposed adjacent to the bottom surface of the substrate body, and includes a plurality of pads. The first bottom protection structure is disposed on the bottom surface of the substrate body, and covers a portion of the bottom circuit layer. The second bottom protection structure is disposed on the bottom surface of the substrate body, and covers a portion of the bottom circuit layer. A second thickness of the second bottom protection structure is greater than a first thickness of the first bottom protection structure.
    Type: Application
    Filed: May 22, 2019
    Publication date: November 28, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Guo-Cheng LIAO, Yi Chuan DING
  • Publication number: 20190363064
    Abstract: A semiconductor device package includes a circuit layer, an electronic component, an electronic component, a first passivation layer and a second passivation layer. The circuit layer has a first surface. The electronic component is disposed on the first surface of the circuit layer. The first passivation layer is disposed on the first surface of the circuit layer. The first passivation layer has a first surface facing away the circuit layer. The second passivation layer is disposed on the first surface of the first passivation layer. The second passivation layer has a second surface facing away the circuit layer. A uniformity of the first surface of the first passivation layer is greater than a uniformity of the second surface of the second passivation layer.
    Type: Application
    Filed: May 25, 2018
    Publication date: November 28, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen-Long LU
  • Publication number: 20190363040
    Abstract: A semiconductor substrate includes a dielectric layer, a first conductive layer, a first barrier layer and a conductive post. The dielectric layer has a first surface and a second surface opposite to the first surface. The first conductive layer is disposed adjacent to the first surface of the dielectric layer. The first barrier layer is disposed on the first conductive layer. The conductive post is disposed on the first barrier layer. A width of the conductive post is equal to or less than a width of the first barrier layer.
    Type: Application
    Filed: May 23, 2018
    Publication date: November 28, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen-Long LU
  • Publication number: 20190355676
    Abstract: A semiconductor device package includes a substrate, a first coil, a dielectric layer and a second coil. The first coil is disposed on the substrate. The first coil includes a first conductive segment and a second conductive segment. The dielectric layer covers the first conductive segment of the first coil and the second conductive segment of the first coil and defines a first recess between the first conductive segment of the first coil and the second conductive segment of the first coil. The second coil is disposed on the dielectric layer. The second coil has a first conductive segment disposed within the first recess.
    Type: Application
    Filed: May 17, 2018
    Publication date: November 21, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shun-Tsat TU, Pei-Jen LO, Yan-Si LIN, Chien-Chi KUO
  • Publication number: 20190355664
    Abstract: An electronic device includes a first substrate, a first conductor, a first insulation layer, a second substrate, a second conductor, a second insulation layer. The first substrate has a first surface. The first conductor is disposed on the first surface of the first substrate. The first insulation layer is on the first conductor. The second substrate has a second surface facing toward the first surface of the first substrate. The second conductor is disposed on the second surface of the second substrate. The second insulation layer is on the second conductor. The first insulation layer is in contact with a sidewall of the second conductor. The second insulation layer is in contact with a sidewall of the first conductor. A coefficient of thermal expansion (CTE) of the first insulation layer is greater than a CTE of the first conductor.
    Type: Application
    Filed: May 21, 2018
    Publication date: November 21, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen-Long LU
  • Publication number: 20190348344
    Abstract: A connection structure is provided. The connection structure includes an intermediate conductive layer, a first conductive layer and a second conductive layer. The intermediate conductive layer includes a first surface and a second surface opposite to the first surface. The intermediate conductive layer has a first coefficient of thermal expansion. The first conductive layer is in contact with the first surface of the intermediate conductive layer. The first conductive layer has a second CTE. The second conductive layer is in contact with the second surface of the intermediate conductive layer. The first conductive layer and the second conductive layer are formed of the same material. One of the first CTE and the second CTE is negative, and the other is positive.
    Type: Application
    Filed: May 8, 2018
    Publication date: November 14, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen-Long LU, Jen-Kuang FANG
  • Publication number: 20190348354
    Abstract: A substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface disposed adjacent to the first surface of the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. A width of the first end of the first conductive via is smaller than a width of the second end of the first conductive via, and a width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via.
    Type: Application
    Filed: May 10, 2018
    Publication date: November 14, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Lin HO, Chih-Cheng LEE