Abstract: A semiconductor package device includes: (1) a die having an active surface, a back surface opposite to the active surface and a lateral surface extending between the active surface and the back surface; (2) a first conductive pillar disposed on the active surface of the die and electrically connected to the die, the first conductive pillar having a top surface facing away from the die and a lateral surface substantially perpendicular to the top surface of the first conductive pillar; (3) a dielectric layer disposed on the active surface of the die and fully covering the lateral surface of the first conductive pillar; and (4) a package body encapsulating the back surface and the lateral surface of the die.

Abstract: A semiconductor package structure includes a substrate, a semiconductor die, a lid and a cap. The semiconductor die is disposed on the substrate. The lid is disposed on the substrate. The cap is disposed on the lid. The substrate, the lid and the cap define a cavity in which the semiconductor die is disposed, and a pressure in the cavity is greater than an atmospheric pressure outside the cavity.

Abstract: A semiconductor device package includes a semiconductor device, an optical conductive pillar, a first encapsulant and a second encapsulant. The semiconductor device includes a pixel. The optical conductive pillar is disposed on the pixel. The first encapsulant has a first thickness and encapsulates the optical conductive pillar. The second encapsulant has a second thickness different from the first thickness.

Abstract: An optical sensor module includes: (1) a lid defining a first chamber and a second chamber isolated from the first chamber; (2) a light emitting component disposed within the first chamber; and (3) a light sensing component disposed within the second chamber; wherein the lid includes a capping substrate and a top of the first chamber and a top of the second chamber are demarcated by the capping substrate, wherein the capping substrate defines a first penetrating hole at the top of the first chamber and a first runner connecting a side wall of the first penetrating hole, and wherein a first lens or a first transmissive panel is formed or disposed in the first penetrating hole and has an extension formed or disposed in the first runner connecting the side wall of the first penetrating hole.

Abstract: A substrate includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer and comprising an interconnection structure, and an interconnection element. The interconnection element extends from the first surface of the first dielectric layer to the second surface of the first dielectric layer and is surrounded by the interconnection structure.

Abstract: A measuring system includes a temperature-variable container, an optical device and an air conditioner. The temperature-variable container includes a transparent plate. The optical device includes a first optical sensor unit and a second optical sensor unit. The air conditioner is disposed between the transparent plate and the optical device.

Abstract: The present disclosure relates to a power amplifier circuit including a current source, a power control circuit, a current mirror and an output circuit. The current source circuit includes a first transistor and a second transistor. A source of the first transistor is connected to a drain of the second transistor and a gate of the first transistor is connected to a source with the second transistor. The power control circuit is connected to a gate of the second transistor. The current mirror circuit is connected to the gate of the first transistor and a source of the second transistor. The output circuit is connected to the current mirror circuit.

Abstract: The present disclosure relates to a logic control circuit including a first inverter and a voltage limiter. The first inverter is connected to a first input voltage. The first inverter includes a first transistor having a first terminal and a second terminal. The second terminal of the first transistor is connected to a ground. The voltage limiter includes a second transistor. The second transistor has a gate connected to a ground, a source connected to the first terminal of the first transistor and a drain connected to a second input voltage.

Abstract: A semiconductor package includes an electrical connection structure. The electrical connection structure includes: a first conductive layer; a second conductive layer on the first conductive layer; and a conductive cap between the first conductive layer and the second conductive layer, the conductive cap having a hardness greater than a hardness of the first conductive layer.

Abstract: A semiconductor package structure includes a first conductive structure, a second conductive structure, a first semiconductor component, a second semiconductor component and a first encapsulant. The first semiconductor component is disposed on the first conductive structure. The first conductive structure includes a first redistribution layer. The second semiconductor component is disposed on the second conductive structure. The second conductive structure includes a second redistribution layer, and the first conductive structure is electrically connected to the second conductive structure. The first encapsulant covers the first semiconductor component and the first conductive structure. A lateral surface of the first conductive structure and a lateral surface of the first encapsulant are non-coplanar.

Abstract: A package device includes a circuit layer, at least one conductive segment, an encapsulant and a redistribution layer. The conductive segment is disposed on the circuit layer and has a first surface and a second surface. The encapsulant encapsulates at least a portion of the conductive segment and has a first upper surface. A first portion of the first surface and at least a portion of the second surface of the conductive segment are disposed above the first upper surface of the encapsulant. The redistribution layer is disposed on the encapsulant, the first portion of the first surface of the conductive segment, and the second surface of the conductive segment.

Abstract: A semiconductor package structure includes a first insulating layer, a first conductive layer, a multi-layered circuit structure, a protection layer, and a semiconductor chip electrically connected to the multi-layered circuit structure. The first insulating layer defines a first through hole extending through the first insulating layer. The first conductive layer includes a conductive pad disposed in the first through hole and a trace disposed on an upper surface of the first insulating layer. The multi-layered circuit structure is disposed on an upper surface of the first conductive layer. The multi-layered circuit structure includes a bonding region disposed on the conductive pad of the first conductive layer and an extending region disposed on the trace of the first conductive layer. The protection layer covers the upper surface of the first insulating layer and the extending region of the multi-layered circuit structure, and exposes the bonding region of the multi-layered circuit structure.

Abstract: A semiconductor package includes a filler composition, wherein the filler composition includes particles each including both carbon and silica, wherein the filler composition is substantially devoid of alumina or silicon carbide, and the filler composition has a weight ratio of carbon to silica of at least greater than 1.0.

Abstract: A substrate includes: (1) a first patterned conductive layer, the first patterned conductive layer including a pair of first transmission lines adjacent to each other; and (2) a first reference layer above the pair of first transmission lines, the first reference layer defining an opening, wherein the pair of first transmission lines are exposed to the opening.

Abstract: An electrical device includes a substrate and a via. The substrate has a first surface and defines a recess in the first surface. The via is disposed in the recess. The via includes an insulation layer, a first conductive layer and a second conductive layer. The insulation layer is disposed on the first surface of the substrate and extends at least to a sidewall of the recess. The first conductive layer is disposed adjacent to the insulation layer and extends over at least a portion of the first surface. The second conductive layer is disposed adjacent to the first conductive layer and extends over at least a portion of the first surface. The second conductive layer has a negative coefficient of thermal expansion (CTE).

Abstract: An optical device package includes: (1) a waveguide, the waveguide including: a main body; and multiple forks, wherein each of the plurality of forks has a tapering end and is extended from the main body, and wherein each of the tapering ends of the forks includes a facet for receiving light; and (2) an optical fiber having a surface configured to output the light into the waveguide; wherein a lateral distance between the surface of the optical fiber and at least one of the facets is less than about 25 micrometers (?m).

Abstract: A semiconductor device package includes a carrier, a first conductive post and a first adhesive layer. The first conductive post is disposed on the carrier. The first conductive post includes a lower surface facing the carrier, an upper surface opposite to the lower surface and a lateral surface extended between the upper surface and the lower surface. The first adhesive layer surrounds a portion of the lateral surface of the first conductive post. The first adhesive layer comprises conductive particles and an adhesive. The first conductive post has a height measured from the upper surface to the lower surface and a width. The height is greater than the width.

Abstract: A method for manufacturing a semiconductor device package includes: (1) providing a first encapsulation layer; (2) disposing an adhesive layer on the first encapsulation layer; (3) disposing a first die on the adhesive layer; and (4) forming a second encapsulation layer covering the first die, the adhesive layer, and the first encapsulation layer.

Abstract: A semiconductor device package includes: (1) an electronic device including an active surface and a contact pad adjacent to the active surface; and (2) a redistribution stack including a dielectric layer disposed over the active surface and defining a first opening exposing at least a portion of the contact pad; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the contact pad, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, and the maximum width of the second portion of the first trace is no greater than 3 times of a width of the first portion of the first trace, wherein the sec

Abstract: A semiconductor device package is provided, which includes a carrier, a first reflective element, a second reflective element, a first optical component, a second optical component and a microelectromechanical system (MEMS) device. The carrier has a first surface. The first reflective element is disposed on the first surface of the carrier. The second reflective element disposed on the first surface of the carrier. The first optical component is disposed on the first reflective element. The second optical component is disposed on the second reflective element. The MEMS device is disposed on the first surface of the carrier to provide light beams to the first reflective element and the second reflective element. The light beams provided to the first reflective element are reflected to the first optical component and the light beams provided to the second reflective element are reflected to the second optical component.