Abstract: An electronic device includes a first dielectric layer, a second dielectric layer and at least one first stud bump. The second dielectric layer is disposed on the first dielectric layer. The first stud bump is disposed in the first dielectric layer and the second dielectric layer. The first stud bump includes a bump portion and a stud portion, and the stud portion is disposed on the bump portion.

Abstract: A semiconductor substrate and a method of manufacturing the same are provided. The semiconductor substrate includes a carrier and a conductive post. The carrier has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The carrier has a through hole extending between the first surface and the second surface. The carrier has a first opening on the lateral surface. The conductive post is disposed within the through hole.

Abstract: An optical system and a method of manufacturing an optical system are provided. The optical system includes a carrier, a light emitter, a light receiver, a block structure and an encapsulant. The light emitter is disposed on the carrier. The light receiver is disposed on the carrier and physically spaced apart from the light emitter. The light receiver has a light detecting area. The block structure is disposed on the carrier. The encapsulant is disposed on the carrier and covers the light emitter, the light receiver and the block structure. The encapsulant has a recess over the block structure.

Abstract: A wiring structure includes an insulating layer and a conductive structure. The insulating layer has an upper surface and a lower surface opposite to the upper surface, and defines an opening extending through the insulating layer. The conductive structure is disposed in the opening of the insulating layer, and includes a first barrier layer and a wetting layer. The first barrier layer is disposed on a sidewall of the opening of the insulating layer, and defines a through hole extending through the first barrier layer. The wetting layer is disposed on the first barrier layer. A portion of the wetting layer is exposed from the through hole of the first barrier layer and the lower surface of the insulating layer to form a ball pad.

Abstract: A semiconductor package includes a semiconductor die, a plurality of conductive bumps, a shielding layer, an encapsulant and a redistribution layer. The semiconductor die has an active surface, a backside surface and a lateral surface. The conductive bumps are disposed on the active surface of the semiconductor die. The shielding layer is disposed on the lateral surface of the semiconductor die. The encapsulant covers the shielding layer, and has a first surface and a second surface opposite to the first surface. The redistribution layer is disposed on the first surface of the encapsulant and electrically connected to the semiconductor die through the conductive bumps. The shielding layer is electrically connected to the redistribution layer.

Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a substrate, an interposer disposed on the substrate, a conductive pillar disposed on the substrate, a first semiconductor device disposed on the interposer and electrically connected to the conductive pillar, a second semiconductor device disposed on the interposer, and an encapsulant surrounding the conductive pillar. The first semiconductor device includes a first conductive pad electrically connected to the interposer. The second semiconductor device includes a second conductive pad electrically connected to the interposer.

Abstract: A semiconductor device package includes a substrate, a first encapsulant and a second encapsulant. The substrate has an optical region and a surface-mount technology (SMT) device region. The first encapsulant includes a first portion disposed on the optical region and covers the optical region and a second portion disposed on the SMT device region and covers the SMT device region. The second encapsulant is disposed on the substrate and covers at least a portion of the second portion of the first encapsulant and a portion of the first portion of the first encapsulant.

Abstract: A test apparatus includes a first insulation housing, a second insulation housing configured to be coupled to the first insulation housing, and a test board including a first portion and a second portion. The first insulation housing and the second insulation housing are configured to cover the first portion of the test board and to expose the second portion of the test board.

Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a first substrate with a first surface and a second surface opposite to the first surface, a second substrate adjacent to the first surface of the first substrate, and an encapsulant encapsulating the first substrate and the second substrate. The first substrate defines a space. The second substrate covers the space. The second surface of the first substrate is exposed by the encapsulant. A surface of the encapsulant is coplanar with the second surface of the first substrate or protrudes beyond the second surface of the first substrate.

Abstract: A semiconductor device package includes a circuit layer, an antenna structure, a first encapsulant and a reflector. The circuit layer has a first surface, a second surface opposite to the first surface and a third surface extended between the first surface and the second surface. The antenna structure is disposed within the circuit layer. The first encapsulant is disposed on the first surface of the circuit layer, the first encapsulant having a surface. The reflector is disposed on the first encapsulant. The third surface of the circuit layer is substantially coplanar with the surface of the first encapsulant.

Abstract: A semiconductor device package includes a substrate and a monolithic encapsulant. The substrate has a first surface, a second surface opposite to the first surface and a plurality of lateral surfaces extending between the first surface and the second surface. The substrate defines a first opening and a second opening that extend between the first surface and the second surface and respectively expose the plurality of lateral surfaces. The monolithic encapsulant includes a first portion disposed on the first surface of the substrate, a second portion disposed on the second surface of the substrate and a third portion disposed within the first opening and the second opening.

Abstract: A semiconductor substrate includes a first dielectric structure and a first circuit layer. The first circuit layer is embedded in the first dielectric structure. The first circuit layer does not protrude from a first surface of the first dielectric structure. The first circuit layer includes at least one conductive segment. The conductive segment includes a first portion adjacent to the first surface of the first dielectric structure and a second portion opposite to the first portion. A width of the first portion of the conductive segment is different from a width of the second portion of the conductive segment.

Abstract: A semiconductor package includes a dielectric layer and a conductive post. The dielectric layer has a first surface and a second surface opposite to the first surface. The conductive post is disposed in the dielectric layer. The conductive post includes a first portion and a second portion disposed above the first portion. The second portion of the conductive post is recessed from the second surface of the dielectric layer.

Abstract: A semiconductor device package includes a carrier, a first semiconductor device disposed on the carrier, a second semiconductor device disposed on the first semiconductor device, a conductive wire electrically connecting the first semiconductor device to the carrier, and an encapsulant encapsulating the first semiconductor device, the second semiconductor device and the conductive wire. The second semiconductor device defines a hole. The encapsulant exposes the hole. An apex of the conductive wire is lower than a surface of the second semiconductor device by a first distance (s). The apex of the conductive wire is spaced from the first surface of the encapsulant by a second distance (t). A first surface of the encapsulant is lower than a surface of the second semiconductor device by a third distance (D). The third distance is less than or equal to a difference between the first distance and the second distance.

Abstract: A semiconductor package may include a substrate; a microelectromechanical device disposed on the substrate; an interconnection structure connecting the substrate to the microelectromechanical device; and a metallic sealing structure surrounding the interconnection structure.

Abstract: A substrate structure includes a wiring structure and a supporter. The wiring structure includes a first dielectric structure, a first circuit layer, a second dielectric structure and a second circuit layer. The first circuit layer is disposed on the first dielectric structure. The second dielectric structure covers the first dielectric structure and the first circuit layer. A pad portion of the first circuit layer is exposed from the first dielectric structure, and the second circuit layer protrudes from the second dielectric structure. The supporter is disposed adjacent to the first dielectric structure of the wiring structure, and defines at least one through hole corresponding to the exposed pad portion of the first circuit layer.

Abstract: A semiconductor package structure includes: (1) a first substrate; (2) at least one first semiconductor element attached to the first substrate; and (3) a second substrate including a plurality of thermal vias and a plurality of conductive vias, wherein one end of each of the thermal vias directly contacts the first semiconductor element.

Abstract: A semiconductor device package includes: (1) a lead frame including a connection element and multiple leads; (2) a package body encapsulating the lead frame, wherein the package body includes a lower surface and an upper surface opposite to the lower surface, the package body includes a cavity exposing at least one of the leads; (3) at least one conductive via disposed in the cavity of the package body, electrically connected to the connection element, and exposed from the upper surface of the package body; and (4) a conductive layer disposed on the upper surface of the package body and the conductive via.

Abstract: A semiconductor package device includes a substrate, an antenna and a conductor. The substrate has an upper surface. The antenna is disposed on the upper surface of the substrate. The conductor is disposed on the upper surface of the substrate and surrounds the antenna. The conductor has a first surface facing toward the antenna and a second surface opposite to the first surface.

Abstract: A semiconductor package structure includes a first patterned conductive layer including a first conductive pad, a second conductive pad and a first conductive trace disposed between the first conductive pad and the second first conductive pad. The first conductive pad defines a recess. The semiconductor package structure further includes a second patterned conductive layer including a third conductive pad. The semiconductor package structure further includes a first stud bump electrically connecting the first conductive pad of the first patterned conductive layer to the third conductive pad of the second patterned conductive layer. The semiconductor package structure further includes a first encapsulation layer disposed between the first patterned conductive layer and the second patterned conductive layer.