Patents Assigned to Advanced Semiconductor Engineering
  • SEMICONDUCTOR DEVICE PACKAGE INCLUDING MULTIPLE SUBSTRATES WITH DIFFERENT FUNCTIONS
    Publication number: 20240258229
    Abstract: The present disclosure provides a semiconductor device package including a first substrate and an adhesive layer. The first substrate has a first surface and a conductive pad adjacent to the first surface. The conductive pad has a first surface exposed from the first substrate. The adhesive layer is disposed on the first surface of the first substrate. The adhesive layer has a first surface facing the first substrate. The first surface of the adhesive layer is spaced apart from the first surface of the conductive pad in a first direction substantially perpendicular to the first surface of the first substrate. The conductive pad and the adhesive layer are partially overlapping in the first direction.
    Type: Application
    Filed: April 9, 2024
    Publication date: August 1, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Yi Chun CHOU
  • SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20240260181
    Abstract: A semiconductor package device includes a first dielectric layer, a first interconnection layer, a second interconnection layer, and a second dielectric layer. The first dielectric layer has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The first interconnection layer is within the first dielectric layer. The second interconnection layer is on the second surface of the first dielectric layer and extends from the second surface of the first dielectric layer into the first dielectric layer to electrically connect to the first interconnection layer. The second dielectric layer covers the second surface and the lateral surface of the first dielectric layer and the second interconnection layer.
    Type: Application
    Filed: April 9, 2024
    Publication date: August 1, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Ze LIN, Chia Ching CHEN, Yi Chuan DING
  • Semiconductor package structure and method of manufacturing the same
    Patent number: 12050350
    Abstract: A semiconductor package structure and a method of manufacturing the same are provided. A semiconductor package structure includes a first electronic component and a light emitter. The photonic component includes a substrate and a first port. The light emitter is disposed over the substrate of the photonic component. The light emitter is configured to emit light through the first port. A coupling loss between the first port of the photonic component and the light emitter is less than 3 dB.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: July 30, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang-Feng You, Yu-Yuan Yeh, Jun-Wei Chen
  • Semiconductor package structure and method for manufacturing the same
    Patent number: 12051658
    Abstract: A semiconductor package structure includes a redistribution structure and an impedance matching device. The redistribution structure includes a first surface, a second surface opposite to the first surface and a circuitless region extending from the first surface to the second surface. The impedance matching device is disposed on the redistribution structure and includes at least one impedance matching circuit aligned with the circuitless region.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: July 30, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yuan Kung, Hung-Yi Lin
  • PACKAGE STRUCTURE
    Publication number: 20240250006
    Abstract: The present disclosure provides a package structure. The package structure includes a die bonding region and a first lead region. The first lead region extends along a first direction. The first direction is along a first edge of the die bonding region. The first lead region includes a first high density lead region and a first low density lead region. The first high density lead region overlaps the first low density lead region in the first direction.
    Type: Application
    Filed: January 19, 2023
    Publication date: July 25, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: I-Jen CHEN
  • OPTOELECTRONIC PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20240250080
    Abstract: An optoelectronic package structure is provided. The optoelectronic package includes a carrier, an electronic component, a photonic component and a first power supply path in the carrier. The carrier includes a first region and the electronic component is disposed over the first region of the carrier. A first power supply path is electrically connects the electronic component.
    Type: Application
    Filed: March 12, 2024
    Publication date: July 25, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jr-Wei LIN, Mei-Ju LU
  • SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20240249988
    Abstract: A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a substrate, an electronic component, an intermediate structure and a protective layer. The electronic component is disposed over the substrate. The intermediate structure is disposed over the substrate and comprises an interposer and a conductive element on the interposer. The protective layer is disposed over the substrate and has an upper surface covering the electronic component and being substantially level with an upper surface of the conductive element.
    Type: Application
    Filed: January 19, 2023
    Publication date: July 25, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Chang CHEN, Wei-Tung CHANG, Jen-Chieh KAO
  • ELECTRONIC DEVICE
    Publication number: 20240250030
    Abstract: An electronic device is provided. The electronic device includes an inductor and a dielectric layer. The inductor includes a first magnetic layer, a conductive trace over the first magnetic layer, and a second magnetic layer over the conductive trace. The dielectric layer includes a first portion between the second magnetic layer and an inclined surface of the first magnetic layer. A substantially constant distance between the second magnetic layer and the inclined surface of the first magnetic layer is defined by the dielectric layer.
    Type: Application
    Filed: January 23, 2023
    Publication date: July 25, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien Lin CHANG CHIEN, Yuan-Chun TAI, Chiu-Wen LEE, Yu-Hsun CHANG, Tai-Yuan HUANG
  • SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE
    Publication number: 20240250053
    Abstract: A semiconductor device includes a semiconductor die having a first surface and a second surface opposite to the first surface, a plurality of first real conductive pillars in a first region on the first surface, and a plurality of supporters in a second region adjacent to the first region. An area density of the plurality of supporters in the second region is in a range of from about 50% to about 100% to an area density of the plurality of first real conductive pillars in the first region. A method for manufacturing a semiconductor package including the semiconductor device is also disclosed in the present disclosure.
    Type: Application
    Filed: March 5, 2024
    Publication date: July 25, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Hsin He HUANG
  • ELECTRONIC DEVICES
    Publication number: 20240250427
    Abstract: The present disclosure provides an electronic device. The electronic device includes an antenna. The antenna includes a first conductive element, a second conductive element, and a switch circuit. The first conductive element is configured to transmit a first signal along a first direction. The second conductive element is configured to transmit a second signal along a second direction different from the first direction. The switch circuit is configured to electrically couple a ground to the first conductive element and/or the second conductive element.
    Type: Application
    Filed: January 23, 2023
    Publication date: July 25, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wei-Hao CHANG, Wei-Chun LEE
  • METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE AND APPARATUS FOR FLATTENING WORKPIECE
    Publication number: 20240249958
    Abstract: A method for manufacturing a semiconductor package and an apparatus for flattening a workpiece are provided. The method includes providing a panel over a stage, wherein the panel includes a lower surface facing the stage and an upper surface opposite to the lower surface; applying a first force to a first region of the upper surface of the panel along at least one direction from the panel toward the stage; and transferring the first force from the first region to a second region of the upper surface of the panel different from the first region.
    Type: Application
    Filed: January 20, 2023
    Publication date: July 25, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ya Fang CHAN, Cong-Wei CHEN, Kuoching CHENG, Shih-Yu WANG
  • Semiconductor device packages and methods of manufacturing the same
    Patent number: 12046523
    Abstract: A semiconductor device package includes a substrate; an electronic component disposed on the substrate; multiple supporting structures disposed on the substrate; and a reinforced structure disposed on the supporting structures and extending in parallel with the substrate.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: July 23, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Electronic device package and method for manufacturing the same
    Patent number: 12046558
    Abstract: An electronic device package includes a substrate, a first semiconductor die, a second semiconductor die and an encapsulant. The substrate includes a first surface, and a second surface opposite to the first surface. The substrate defines a cavity recessed from the first surface. The first semiconductor die is disposed in the cavity. The second semiconductor die is disposed over and electrically connected to the first semiconductor die. The encapsulant is disposed in the cavity of the substrate. The encapsulant encapsulates a first sidewall of the first semiconductor die, and exposes a second sidewall of the first semiconductor die.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: July 23, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Mei-Ju Lu, Jr-Wei Lin
  • OPTICAL DEVICE PACKAGE
    Publication number: 20240243207
    Abstract: An optical device package is provided. The optical device package includes a sensor and a light-transmitting region. The sensor includes a sensing region. The light-transmitting region is at least partially in the sensor, and the light-transmitting region allows an external light to transmit therethrough and reach the sensing region. A width of the light-transmitting region adjacent to a level of the sensing region is equal to or smaller than a width of the sensing region.
    Type: Application
    Filed: January 12, 2023
    Publication date: July 18, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsiang-Cheng TSAI, Ying-Chung CHEN, Kuo-Hua LAI
  • OPTICAL MODULE
    Publication number: 20240237907
    Abstract: An optical module is disclosed. The optical module includes a carrier, an optical device disposed over the carrier, and a sensing surface facing away from the carrier. The sensing surface includes a transmissive region and a non-transmissive region adjacent to the transmissive region.
    Type: Application
    Filed: January 12, 2023
    Publication date: July 18, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shih-Chieh TANG, Hsun-Wei CHAN, Hsin-Ying HO
  • PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20240243039
    Abstract: At least some embodiments of the present disclosure relate to an electronic structure. The package structure includes a lead frame, an electronic component, and a conductive wire physically and electrically connecting the electronic component to the lead frame. An elevation of a first end of the conductive wire is substantially equal to an elevation of a second end of the conductive wire.
    Type: Application
    Filed: January 18, 2023
    Publication date: July 18, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Ying-Chung CHEN
  • ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20240243086
    Abstract: An electronic device is disclosed. The electronic device includes a chip, a component, and a plurality of first interlayer elements. The chip has an upper surface and a first pad disposed over the upper surface. The component is disposed over the electronic component and configured to filter noise from the electronic component. The plurality of first interlayer elements connect the first pad.
    Type: Application
    Filed: January 18, 2023
    Publication date: July 18, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Sheng-Hsiang HSU, Cheng-Hung KO, Jan-Feng YEN
  • Substrate structure and method for manufacturing the same
    Patent number: 12040261
    Abstract: A substrate structure includes a wiring structure, a first bump pad, a second bump pad and a compensation structure. The wiring structure includes a plurality of redistribution layers. The first bump pad and the second bump pad are bonded to and electrically connected to the wiring structure. An amount of redistribution layers disposed under the first bump pad is greater than an amount of redistribution layers disposed under the second bump pad. The compensation structure is disposed under the second bump pad.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: July 16, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Syu-Tang Liu, Tsung-Tang Tsai, Huang-Hsien Chang, Ching-Ju Chen
  • Optical device including an optical component an electrical component, assembly structure including an optical component an electrical component and method for manufacturing the same
    Patent number: 12040321
    Abstract: An optical device includes an optical component and an electrical component. The optical component has a sensing surface and a backside surface opposite to the sensing surface. The electrical component is disposed adjacent to the backside surface of the optical component and configured to support the optical component. A portion of the backside surface of the optical component is exposed from the electrical component.
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: July 16, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsiang-Cheng Tsai, Ying-Chung Chen
  • Semiconductor device package and method for manufacturing the same
    Patent number: 12040287
    Abstract: A semiconductor device package and method for manufacturing the same are provided. The semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, and a first circuit layer disposed on the substrate. The first circuit layer includes a conductive wiring pattern, and the conductive wiring pattern is an uppermost conductive pattern of the first circuit layer. The stress buffering structure is disposed on the first conductive structure. The second conductive structure is disposed over the stress buffering structure. The conductive wiring pattern extends through the stress buffering structure and electrically connected to the second conductive structure, and an upper surface of the conductive wiring pattern is substantially coplanar with an upper surface of the stress buffering structure.
    Type: Grant
    Filed: October 10, 2022
    Date of Patent: July 16, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsing Kuo Tien, Chih-Cheng Lee