Patents Assigned to Analog Devices, Inc.
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Patent number: 6985024Abstract: A voltage multiplier has a first stage that multiplies an input voltage, and a second stage that multiplies the output of the first stage. To that end, the voltage multiplier has the noted first stage having an input to receive the input voltage, and the second stage in series with the first stage. As noted above, the first stage is capable of multiplying the input voltage by a first amount to produce a first stage output voltage. The second stage thus has an input to receive the first stage output voltage. After receipt, the second stage is capable of multiplying the first stage output voltage by a second amount to produce a second stage output voltage.Type: GrantFiled: August 21, 2003Date of Patent: January 10, 2006Assignee: Analog Devices, Inc.Inventor: John A. Geen
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Patent number: 6984969Abstract: A voltage regulator includes a linear mode regulator having a high pass filter circuit connected between its output and an output node, and a switch mode regulator having an low pass filter circuit connected between its output and the same output node. The high pass filter passes high frequency AC current provided by the linear mode regulator to the output node and reduces the low frequency AC and DC currents to substantially zero, and the low pass filter prevents the high frequency AC current produced by the linear mode regulator from being drawn by the switch mode regulator and passes the low AC and DC currents provided by the switch mode regulator to the output node. Thus, the present regulator offers the high response speed and low noise of a linear mode regulator, and the high power efficiency and large continuous output current capability of a switch mode regulator.Type: GrantFiled: March 19, 2004Date of Patent: January 10, 2006Assignee: Analog Devices, Inc.Inventors: Gang Liu, Joseph C. Buxton, Paul R. Collanton, Jr.
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Patent number: 6986026Abstract: In one embodiment, techniques are disclosed for causing a programmable processor to process one instruction at a time. Single-step debugging may be performed by taking an exception after each instruction or by invoking emulation mode after each instruction. The particular single-step debugging technique may be based upon state of control bits, or may be based upon the processor's current mode of operation, or both.Type: GrantFiled: December 15, 2000Date of Patent: January 10, 2006Assignees: Intel Corporation, Analog Devices, Inc.Inventors: Charles P. Roth, Ravi P. Singh, Tien Dingh, Ravi Kolagotla, Marc Hoffman, Russell Rivin
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Patent number: 6985100Abstract: A multi-channel integrated circuit comprises a plurality of channels (CH1 to CH20). A DAC (3) is provided in each channel (CH1 to CH20) for converting digital data inputted to the circuit (1) through an I/O port (14). Digital data to be converted by the DACs (3) is selectively applied to input registers (10) of each channel (CH1 to CH20) on a digital data bus (16) under the control of an interface and control logic circuit (15). The digital words written to the input registers (10) are in turn written to DAC registers (9) through corresponding digital switches (12) for conversion by the DACs (3). A clear code register (22) stores a clear code for writing to the DAC registers (9) in response to a clear signal applied to a clear terminal (24) of the circuit (1) so that analogue outputs appearing on output terminals (5) of the channels (CH1 to CH20) are of a predetermined value, typically, zero volts, when the circuit (1) is set in a clear condition.Type: GrantFiled: December 9, 2003Date of Patent: January 10, 2006Assignee: Analog Devices, Inc.Inventors: Donal P. Geraghty, Denis Martin O'Connor, Dennis Arnold Dempsey
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Publication number: 20060001413Abstract: A proportional to absolute temperature voltage circuit. A voltage circuit including a first amplifier having first and second inputs and having an output driving a current mirror circuit is provided. Outputs from the current mirror circuit drive first and second transistors which are coupled to the first and second input of the amplifier respectively. The base of the first transistor is coupled to the second input of the amplifier and the collector of the first transistor is coupled to the first input of the amplifier such that the amplifier keeps the base and collector of the first transistor at the same potential. The first and second transistors are adapted to operate at different current densities such that a difference in base emitter voltages between the first and second transistors may be generated across a resistive load coupled to the second transistor, the difference in base emitter voltages being a PTAT voltage.Type: ApplicationFiled: June 30, 2004Publication date: January 5, 2006Applicant: Analog Devices, Inc.Inventor: Stefan Marinca
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Publication number: 20060001563Abstract: A programmable input voltage range analog-to-digital converter in which a split gate oxide process allows the use of high voltage (±15 volt) switches on the same silicon substrate as standard sub-micron 5 volt CMOS devices. With this process, the analog input voltage can be sampled directly onto one or more sampling capacitors without the need for prior attenuation circuits. By only sampling on a given ratio of the sampling capacitors, the analog input can be scaled or attenuated to suit the dynamic range of a subsequent ADC. In the system of the present invention, the sampling capacitor can be the actual capacitive redistribution digital-to-analog converter (CapDAC) used in a SAR ADC itself, or a separate capacitor array. By selecting which bits of the CapDAC or separate sampling array to sample on, one can program the input range.Type: ApplicationFiled: September 1, 2005Publication date: January 5, 2006Applicant: Analog Devices, Inc.Inventor: Thomas Kearney
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Patent number: 6982664Abstract: Timing enhancements of embodiments of the invention are realized in time-interleaved converter systems with minimal network additions that facilitate the insertion of a timing signal into the system's input analog signal. The timing signal travels with the input analog signal so that it continues to accurately define predetermined sample times in the analog signal even as they travel over different path lengths to individual converters. Each converter has a feedback path which adjusts the timing of that converter's samples with a correction signal whose value is determined by contributions of first and second different amplitudes of the timing signal to that converter's output signals.Type: GrantFiled: November 4, 2004Date of Patent: January 3, 2006Assignee: Analog Devices, Inc.Inventor: David G. Nairn
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Patent number: 6981122Abstract: A memory system and a method for operating a memory system are provided. The memory system includes a set of memory banks, logic for calculating a first address in each memory bank from the set of memory banks and a controller receiving a transfer address from a computing device. The controller includes logic for selecting a memory bank from the set of memory banks based on the transfer address and the first addresses of the memory banks, and for mapping the transfer address to a target address in the selected memory bank based on a first address in the selected memory bank. As a result, the set of memory banks has a contiguous memory space.Type: GrantFiled: September 26, 2002Date of Patent: December 27, 2005Assignee: Analog Devices, Inc.Inventors: Thomas A. Volpe, Michael S. Allen, Aaron Bauch
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Patent number: 6981195Abstract: Efficient re-computation of an error detection code is achieved with an original data message that includes a payload and an error detection code. The error detection code comprises a value determined according to an error detection formula using the payload. The payload is modified using a payload transformation formula. The error detection code is re-computed from the original error detection code, rather than from the modified payload. The formula for re-computing the error detection code is different from the formula used to originally obtain the error detection formula, and does not use the original payload or the modified payload.Type: GrantFiled: August 2, 2002Date of Patent: December 27, 2005Assignee: Analog Devices, Inc.Inventors: Dalton J. Newcombe, Tilaye Terrefe
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Patent number: 6978350Abstract: Methods and apparatus are provided for operating an embedded processor system that includes a processor and a cache memory. The method includes filling one or more lines in the cache memory with data associated with a first task, executing the first task, and, in response to a cache miss during execution of the first task, performing a cache line fill operation and, during the cache line fill operation, executing a second task. The cache memory may notify the processor of the line fill operation by generating a processor interrupt or by notifying a task scheduler running on the processor.Type: GrantFiled: August 29, 2002Date of Patent: December 20, 2005Assignee: Analog Devices, Inc.Inventors: Palle Birk, Joern Soerensen, Michael S. Allen, Jose Fridman
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Publication number: 20050275445Abstract: A voltage level translator provides an output signal having an external voltage in response to an input signal having an internal voltage. The voltage level translator includes first and second input signal transistors, first and second output signal transistors, and includes a signal stabilization circuit and/or an enable circuit. A ready-signal generation circuit provides a ready signal indicating that a voltage supply is at an operating voltage. The ready-signal generation circuit can include unbalanced transistors.Type: ApplicationFiled: August 17, 2005Publication date: December 15, 2005Applicant: Analog Devices, Inc.Inventors: Brian Johansson, Stuart Patterson
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Patent number: 6975253Abstract: The proposed technique uses basic properties of a Huffman codebook to decode a coded data bit stream having a plurality of variable length codewords based on the Huffman codebook. This is achieved by sorting codewords in the Huffman codebook based on potential values. The potential values are computed using the basic parameters of the codewords in the Huffman codebook. A current bit sequence having a predetermined length is extracted from the coded data bit stream. A potential value of the extracted bit sequence is then computed using the basic parameters of the codewords in the Huffman codebook. The sorted Huffman codebook is then searched to find a computed potential value in the sorted Huffman codebook that is substantially close to the computed potential value of the extracted bit sequence. The extracted current bit sequence is decoded based on the outcome of the search.Type: GrantFiled: August 6, 2004Date of Patent: December 13, 2005Assignee: Analog Devices, Inc.Inventor: Pushparaj Dominic
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Patent number: 6976151Abstract: In one embodiment, a processor receives coded instructions and converts the instructions to a second code prior to execution. The processor may be a digital signal processor. A decoder in the processor determines the destination of the instructions and performs decoding functions based on the destination.Type: GrantFiled: September 28, 2000Date of Patent: December 13, 2005Assignees: Intel Corporation, Analog Devices, Inc.Inventors: Gregory A. Overkamp, Charles P. Roth, Ravi P. Singh
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Patent number: 6975950Abstract: Methods and apparatus for calibrating one or more signals of an electronic device are provided. Calibration coefficients are stored in a memory, such as a fuse bank, to be applied to correct the one or more signals. A selection multiplexer is provided, the selection multiplexer capable of assigning one of a number of bit weight configurations to the calibration coefficients to set a desired range and resolution for calibration information applied to the one or more signals of the electronic device.Type: GrantFiled: December 18, 2003Date of Patent: December 13, 2005Assignee: Analog Devices, Inc.Inventor: Scott G. Bardsley
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Patent number: 6970124Abstract: Comparator systems are provided that include first and second differential pairs of transistors with inherent offsets that are a function of their tail currents. Some system embodiments configure the pairs to have substantially-equal, nonzero inherent offset voltages and other embodiments configure them to have substantially-zero inherent offset voltages. The systems further include a feedback network arranged to provide a second tail current to the second differential pair that substantially nulls the second output signal of this differential pair when it is driven by a reference signal. The feedback network generates an identical first tail current for the first differential pair which will now accurately compare an input signal to the reference signal.Type: GrantFiled: February 11, 2005Date of Patent: November 29, 2005Assignee: Analog Devices, Inc.Inventor: Gregory Wayne Patterson
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Patent number: 6969985Abstract: A coupler circuit for sampling an output power of a signal from an output power source has at least one first sampling element for sampling a first portion of the signal and at least one second sampling element for sampling a second portion of the signal. The first sampling element and the second sampling element are separated by an output matching network defined by a set of S-parameters. A processor coupled to the at least one first and second sampling elements determines the output power based on at least the first portion of the signal and the second portion of the signal. A detector may be coupled to the processor to measure whether the first and second portion of the signal or the output power determined by the processor.Type: GrantFiled: December 14, 2001Date of Patent: November 29, 2005Assignee: Analog Devices, Inc.Inventor: Robert J. McMorrow
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Patent number: 6970126Abstract: A variable capacitance switched capacitor input system and method includes a differential integrator circuit having first and second input summing nodes and a variable sensing capacitor; one terminal of the variable sensing capacitor is connected to one of the nodes in the first phase and to the other of the nodes in the second phase; an input terminal connected to a second terminal of the variable sensing capacitor receives a first voltage level in the first phase and a second voltage level in the second phase for delivering the charge on the variable sensing capacitor to the first summing node in the first phase and to the second summing node in the second phase and canceling errors in a differential integrator circuit output caused by leakage current.Type: GrantFiled: June 25, 2004Date of Patent: November 29, 2005Assignee: Analog Devices, Inc.Inventors: John O'Dowd, Damien McCartney
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Publication number: 20050258904Abstract: Methods and apparatus for amplifying a tuner input signal are disclosed. One embodiment of the invention is directed to a tuner amplifier system comprising a tuner amplifier input that receives a tuner amplifier input signal and a first amplifier comprising an input and an output. The input of the first amplifier is coupled to the tuner amplifier input. The system further comprises a second amplifier comprising an input and an output, the input of the second amplifier being coupled to the tuner amplifier input, and a switch adapted to couple one of the first amplifier output and the second amplifier output to an output of the tuner amplifier. Another embodiment of the invention is directed to a method of amplifying a tuner input signal. The method comprises acts of detecting a power of the tuner input signal, selecting a tuner amplifier to amplify the tuner input signal based on the power of the tuner input signal, and amplifying the tuner input signal using the selected amplifier.Type: ApplicationFiled: May 20, 2004Publication date: November 24, 2005Applicant: Analog Devices, Inc.Inventor: Iuri Mehr
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Publication number: 20050259186Abstract: Methods and apparatus for tuning are disclosed. One embodiment of the invention is directed to a tuner formed on a substrate. The tuner comprises a first die that receives an analog input signal and processes the analog input signal using analog processing circuitry to form analog output signals, and a second die that receives the analog output signals, converts the analog output signals to digital signals, and processes the digital signals to form output signals. Another embodiment of the invention is directed to a multi-chip module comprising a tuner adapted to process television signals of a plurality of types and of a plurality of standards to form output signals.Type: ApplicationFiled: May 20, 2004Publication date: November 24, 2005Applicant: Analog Devices, Inc.Inventors: Iuri Mehr, Sergei Nesterenko, Richard Schreier, David Robertson
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Publication number: 20050258789Abstract: A drive circuit for a brushless DC motor includes a switch constructed and arranged to drive the motor with a pulse signal responsive to a control signal, and control circuitry coupled to the switch and constructed and arranged to generate the control signal responsive to rotor position information from the motor so as to synchronize the pulse signal to the rotor position. A current sensing device can be used to provide the rotor position information to the control circuitry by sensing current flowing through the motor.Type: ApplicationFiled: July 25, 2005Publication date: November 24, 2005Applicant: Analog Devices, Inc.Inventors: Robin Getz, David Hanrahan