Abstract: Embodiments provide for a method for eliminating pathological sequences in a serial bit stream. Parallel data words having a first bit length are received. The received data words may be analyzed for a pathological sequence. If a pathological sequence is present in a data word, the data word containing the pathological sequence may be segmented into data segments having bit lengths less than a pathological sequence. The data word may be reformatted by generating reformatted data words having a second bit length. The reformatted data words may contain at least one of the data segments and the second bit length is greater than the first bit length. The reformatting may be performed by adding framing bits to the segments to form the reformatted data words. The reformatted data words are transmitted in place of the data word containing the pathological sequence.

Abstract: An apparatus and a method for providing serialized HDMI data from an HDMI source to an HDMI sink. An HDMI transmitter may include inputs including control inputs, a deserializer, and a parser. The inputs may receive serialized HDMI data from an HDMI data source. A deserializer may deserialize the serialized HDMI data received on each of the respective inputs and outputting parallel data for each of the inputs. A parser may parse the parallel data output from the deserializer from each of the respective inputs into serial video data at a first clock rate and audio data at a second clock rate. Control inputs of the transmitter may be set to a first mode in which from the deserializer is caused to bypass the parser, and the parallel data is output from the HDMI transmitter.

Abstract: A digital to analog converter (DAC) includes a pair of operational amplifiers each having a first input coupled to a respective high or low reference voltage. The DAC includes a plurality of switch-controlled cells, each of which includes a resistor and two force/sense switch pairs. Within each cell, all four switches are coupled to the resistor. A first force switch is coupled to an output of a first op amp and an associated sense switch is coupled to an inverting input of the first op amp. A second force switch is coupled to an output of a second op amp and an associated sense switch is coupled to an inverting input of the second op amp. Thus, the force switches provide selectively conductive paths to permit either op amp to drive a given cell.

Abstract: Organic anti-stiction coatings such as, for example, hydrocarbon and fluorocarbon based self-assembled organosilanes and siloxanes applied either in solvent or via chemical vapor deposition, are selectively etched using a UV-Ozone (UVO) dry etching technique in which the portions of the organic anti-stiction coating to be etched are exposed simultaneously to multiple wavelengths of ultraviolet light that excite and dissociate organic molecules from the anti-stiction coating and generate atomic oxygen from molecular oxygen and ozone so that the organic molecules react with atomic oxygen to form volatile products that are dissipated, resulting in removal of the exposed portions of the anti-stiction coating. A hybrid etching process using heat followed by UVO exposure may be used. A shadow mask (e.g., of glass or quartz), a protective material layer, or other mechanism may be used to selective expose the portions of the anti-stiction coating to be UVO etched.

Abstract: A most significant bits analog to digital converter for determining a first P bits of an N bit analog to digital conversion, the most significant bits analog to digital converter comprising: a digital to analog converter a capacitive attenuator, and a switching arrangement for inhibiting action of the attenuator during sampling and enabling the attenuator during conversion.

Abstract: A high performance follower device coupled with a slew enhancement circuit includes an amplifier circuit containing a follower device connected to a three-terminal device, whereupon current drawn through the three-terminal device is amplified through a current amplifier and sent to the source terminal of the follower device to stabilize the output voltage when the input signal is changed rapidly or if the output voltage is disturbed by a changing output load. The presence of a cascode device also allows for the bootstrapping of the follower device.

Abstract: In one aspect, a calibration component configured to calibrate an automatic gain controller (AGC) for use in a tuner configured to isolate a selected channel from a multi-channel broadcast signal, the tuner implemented substantially on two chips, a first chip comprising a radio frequency (RF) integrated circuit adapted for RF processing and a second chip comprising a digital integrated circuit adapted for digital processing is provided.

Abstract: A reference voltage generator circuit may include at least one MOS transistor and at least one bipolar transistor coupled together to provide an electrical path from an input reference potential to an output of the generator circuit. The electrical path may extend through a gate-to-source path of the MOS transistor and further through a base-to-emitter path of the bipolar transistor. The MOS transistor may be biased by a bias current that is proportional to T2·?(T), where T represents absolute temperature and ?(T) represents mobility of a MOS transistor in the bias current generator. Optionally, the reference voltage generator may include N MOS and M multiple bipolar transistors (N?1, M?1), and the output reference voltage may be N*VGS+M*VBE as compared to the input reference potential.

Abstract: A switch control circuit monitors a signal produced by a MEMS or other capacitor microphone. When a criterion is met, for example when the amplitude of the monitored signal exceeds a threshold or the monitored signal has been clipped or analysis of the monitored signal indicates clipping is imminent or likely, the switch control circuit operates one or more switches so as to selectively connect one or more capacitors to a signal line from the microphone, i.e., so as to connect a selected capacitance to the signal line to attenuate the signal from the microphone and, therefore, avoid clipping. The switches may be MOSFET, MEMS or other types of switches co-located with the microphone in a common semiconductor package. Similarly, the capacitors, a circuit that processes the signals from the microphone and/or the switch control circuit may be co-located with the microphone in a common semiconductor package.

Abstract: Synthesizers are configured with first and second phase-locked loops (PLL's). The first PLL is arranged to include a digitally-controlled oscillator (DCO) and to respond to an input signal to provide a reference signal with a plurality of selectable reference frequencies. The second PLL is arranged to include a voltage-controlled oscillator (VCO) to thereby provide output signals in response to the reference signal. This synthesizer structure is particularly effective when responding to a noisy input signal as may be the case, for example, in wireless communication systems that provide a network clock to transceivers through lengthy optical links.

Abstract: Error amplifier structures are provided to generate an error signal in response to the difference between an input signal (e.g., a feedback current) and a reference signal (e.g., a bias current). Amplifier embodiments generally include a reference generator and a differencing amplifier. In at least one embodiment, the error generator is arranged to generate first and second bias voltages that correspond to the bias current. In at least one embodiment, the differencing amplifier is configured to provide a reference current to an output node in response to the first bias voltage, provide a feedback current to the output node in response to the second bias voltage, and generate an error current in response to a voltage at the output node. The error amplifier structures are suited for use in various systems such as negative switching regulators.

Abstract: A system for correcting duty cycle errors in a clock receiver that includes a differential amplifier having inputs for a pair of differential clock signals. A duty cycle error detector has inputs for a pair of amplified clock signals and an output for a duty cycle error correction signal. A signal conditioner is also provided with the differential amplifier having an input for the duty cycle error correction signal. Furthermore, the signal conditioner adjusts the differential clock signals in response to the duty cycle error correction signal. Also, a system for correcting cross point errors in a clock receiver that includes a differential amplifier having inputs for a pair of differential clock signal. A cross point error detector has inputs for a pair of amplified clock signals and an output for a cross point error correction signal. A signal conditioner is also provided with the differential amplifier having an input for the cross point error correction signal.

Abstract: Methods and apparatus for amplifying signals over a wide frequency range to generate high voltage outputs feature a pair of switching modules which are connected in series. Switching modules, e.g., field-effect transistors (FETs), operate based on the voltage difference between an amplified signal and a fixed DC signal at two of their terminals, thereby generating an output waveform that has peak-to-peak voltage higher than, e.g. twice, the breakdown voltage of the transistors within the amplifier. The DC signals applied at the switching modules may be varied using an AC signal to improve the risetime of the output waveform and achieve a faster operational speed of the amplifier.

Abstract: A system for randomizing aperture delay in a time interleaved ADC system that includes a plurality of selection switch stages corresponding to each of the ADCs in the system and a second selection switch stage coupled to a voltage source. A plurality of conductors extend between the second selection switch stage and each of the selection switch stages, in excess of the number of ADCs in the system. For each of N ADCs in the system, the selection switch stages and the second selection switch stage support at least N+1 selectable conductive paths extending from each of the sampling capacitors of the ADCs to the voltage source. Random selection of the N+1 paths can randomize aperture delay.

Abstract: A mode matching servo for an inertial sensor having a resonator and an accelerometer provides a test signal at a frequency higher than a predetermined inertial sensor response frequency and lower than an accelerometer resonance mode frequency so as to induce acceleration signals from the accelerometer substantially at the test signal frequency when the modes are not matched. A feedback signal is provided in response to such induced signals to substantially nullify the signals.

Abstract: A ?-type voltage-controlled variable attenuator is disclosed. The variable attenuator may include variably resistive components in the series and shunt arms. The variably resistive components may be implemented as field effect transistors. The shunt arms may be coupled to the series arm, and the variable attenuator may lack capacitors between the series arm and shunt arms. The series arm and shunt arms may display variable resistances which, in combination, operate to provide a variable level of attenuation of an input signal. The variable attenuator may provide any level of attenuation of an input signal over a wide frequency range. The variable attenuator may be implemented as an integrated circuit.

Abstract: The analog-to-digital for converter (ADC) for converting an analog value into a digital equivalent using a parallel digital data path is disclosed. In one example embodiment, the ADC includes a switched capacitor DAC having an input to receive an analog value via analog sample and hold circuit. A comparator is coupled to the switched capacitor DAC. A successive approximation register (SAR) is coupled to the comparator. A plurality of logic blocks is coupled to the SAR. A plurality of thermometric encoders is coupled to the associated plurality of logic blocks. A plurality of MUXs is coupled to the associated plurality of thermometric encoders and the comparator, wherein the plurality of MUXs having associated outputs that is coupled to the input of the switched capacitor DAC.

Abstract: A method of forming a microphone having a variable capacitance first deposits high temperature deposition material on a die. The high temperature material ultimately forms structure that contributes to the variable capacitance. The method then forms circuitry on the die after depositing the deposition material. The circuitry is configured to detect the variable capacitance.

Abstract: An SAR analog-to-digital converter performs bit decisions in each of a plurality of clock cycles. A sense circuit monitors signals input to a latch within a comparator of the ADC and, when the signals are sufficient to establish a bit decision, the sense circuit terminates a currently active clock cycle causes a bit decision to occur in advance of a normal expiration of the clock cycle. If the signals are insufficient to establish a bit decision prior to a default expiration time of the clock cycle, the clock cycle concludes at the default expiration time.

Abstract: Synchronous analog to digital conversion including providing a voltage analog to digital converter and a current analog to digital converter, synchronizing the converters, providing a signal conditioning circuit associated with the input of each converter, providing a current input to one of the signal conditioning currents and a voltage input to the other; and processing the inputs with gains differing by substantially an order of magnitude with substantially balanced time delays; and providing those conditioned inputs to the associated converters.