Abstract: A digital to analog converter (DAC) includes a pair of operational amplifiers each having a first input coupled to a respective high or low reference voltage. The DAC includes a plurality of switch-controlled cells, each of which includes a resistor and two force/sense switch pairs. Within each cell, all four switches are coupled to the resistor. A first force switch is coupled to an output of a first op amp and an associated sense switch is coupled to an inverting input of the first op amp. A second force switch is coupled to an output of a second op amp and an associated sense switch is coupled to an inverting input of the second op amp. Thus, the force switches provide selectively conductive paths to permit either op amp to drive a given cell.

Abstract: Proximity detection is accomplished by determining with a moving average calculation a moving average level of input data; setting a threshold level in response to the average level and a sensitivity factor; producing a proximity detection output when the input data meets the threshold level; and changing the weighting used by the average level calculation in response to a proximity detection output.

Abstract: A circuit can include an NMOS transistor having a drain and a source, a p-well containing the drain and the source, an n-well under the p-well, a circuit node, and a connection element connecting the n-well to the circuit node. The connection element can include a diode having an anode terminal connected to the circuit node and a cathode terminal connected to the n-well, a resistor having a first terminal connected to the circuit node and a second terminal connected to the n-well, a conductor directly connecting the n-well to the circuit node, or a well switch configured to connect the n-well to the circuit node during an enable phase of a switching signal and to electrically float the n-well during a non-enable phase of the switching signal. The diode can include a diode-connected transistor. The circuit node can be configured to receive a predetermined voltage having a magnitude equal to or greater than an upper supply voltage.

Abstract: A bandgap voltage reference circuit which provides a bandgap reference voltage without requiring a resistor. The circuit comprises an amplifier having an inverting input, a non-inverting input and an output. First and second bipolar transistors are provided which operate at different current densities each coupled to a corresponding one of the inverting and non-inverting inputs of the amplifier. A load MOS transistor of a first aspect ratio is driven by the amplifier to operate in the triode region with a corresponding drain-source resistance ron. The load MOS device is operably coupled to the second bipolar transistor such that a base-emitter difference (?Vbe) resulting from the collector current density difference between the first and second bipolar transistors is developed across the drain-source resistance ron, of the load MOS device. A cascoded MOS device of a second aspect ratio is operably coupled to the load MOS device and is driven by the amplifier to operate in the triode region.

Abstract: An integrated circuit includes a substrate, a storage device formed in the substrate to hold bias settings, and operational blocks formed in the substrate, each operational block including an operational circuit and a charge pump to provide well bias voltages to the operational circuit in response to one or more of the bias settings. A method for testing an integrated circuit having two or more operational blocks includes: (a) determining a maximum operating speed of each of the blocks at a minimum supply voltage; (b) selecting a block that has a slow operating speed; (c) selecting a well bias to speed up the selected block; (d) selecting a supply voltage to meet a target operating frequency at the selected well bias and measuring power; (e) repeating acts (b)-(d) while the measured power is less than a baseline power; and (f) saving the selected well bias and supply voltage settings for operation of the integrated circuit.

Abstract: An amplifier includes an amplifier section having selectable signal paths to provide discrete gain settings, and logic to incrementally select the signal paths. The logic may be configured to increment the gain in response to digital gain control signals or an analog gain control signal. Another amplifier has an input section with one or more input cells and an output section with one or more output cells. Either the input section or the output section includes at least two cells that may be selected to provide discrete gain settings. A loop amplifier is configured in a feedback arrangement with the input section. The input and output sections may have multiple selectable cells to provide coarse and fine gain steps. The gain of the loop amplifier may be coordinated with the gain of the input section to provide constant bandwidth operation.

Abstract: An electronics package has a wafer level chip scale package (WLCSP) die substrate containing electronic circuits. Through-silicon vias through the die substrate electrically connect the electronic circuits to the bottom surface of the die substrate. A package sensor is coupled to the die substrate for sensing an environmental parameter. A protective encapsulant layer covers the top surface of the die substrate. A sensor aperture over the package sensor provides access for the package sensor to the environmental parameter.

Abstract: A class G headphone amplifier circuit with improved power efficiency and low EMI. It may use an automatic signal level detector to detect the signal level of incoming signals and determine positive and negative power supplies for headphone amplifiers accordingly. A voltage generator may generate pairs of differential output voltages at a plurality of amplitude steps, and supply to headphone amplifiers the pair with the amplitude determined by the automatic signal level detector. As a result, headphone amplifiers are biased according to the input signal level, and the multiple voltage rails may improve power efficiency and avoid clipping.

Abstract: A compute unit with an internal bit FIFO circuit includes at least one data register, a lookup table, a configuration register including FIFO base address, length and read/write mode fields for configuring a portion of the lookup table as a bit FIFO circuit and a read/write pointer register responsive to an instruction having a lookup table identification field, length of bits field and register extract/deposit field for selectively transferring in a single cycle between the FIFO circuit and the data register a bit field of specified length.

Abstract: Disclosed are a method, device, and system for a microelectromechanical (MEM) device control system that can control the operation of a MEM device. The system can include a microelectromechanical device and a control circuit. The micromechanical device can include a moveable member coupled to an electrical terminal, a sensor, responsive to a movement of the moveable member, can output a sensor signal based on the movement of the moveable member, and an actuating electrode for receiving a control signal. The control circuit can be responsive to the signals output by the sensor and outputs the control signal to the actuating electrode.

Abstract: Finite impulse response filtering is achieved by broadcasting to at least one compute unit an instruction having a plurality of data samples, a conditional field associated with each compute unit, and a set of operator values for operating on each data sample; providing a function of each the data sample in accordance with an associated set of operator values identified by the conditional field; and combining the functions to obtain an intermediate finite impulse response of the data samples.

Abstract: Noise reduction for a switching amplifier system having a differential output stage and demodulator filter responsive to complementary PWM signals includes generating in-phase PWM signals and gradually adjusting their duty cycle between a low duty cycle and the full duty cycle of the complementary PWM signals, generating full duty cycle PWM signals and gradually shifting their relative phase between in-phase and out-of-phase; and in response to a turn-on signal, adjusting the in-phase PWM signals from low to full duty cycle and shifting the relative phase from in-phase to out-of-phase, and in response to a turn-off signal shifting the relative phase from out-of-phase to in-phase and adjusting the in-phase PWM signals from full to low duty cycle for maintaining balanced charge on the demodulation filter to reduce audible noise.

Abstract: Various methods are described where the semiconductor die and the lead frame (or the BGA or LGA substrate) are spaced apart to reduce stress. In one scenario, an air gap is formed between the semiconductor die and the lead frame by depositing a perimeter (made, for example, using polymer) either on the semiconductor die or the lead frame. In another scenario, an anisotropic conducting film (ACF) is formed with an air gap between the semiconductor die and the lead frame (or the BGA or LGA substrate). The air gap relieves stress on the semiconductor die. Further, a lead frame-based isolator package and a BGA (or LGA) isolator package are described. A window-frame ACF-based isolation method for magnetic coupling in a lead-frame package and BGA (or LGA) package is also described.

Abstract: Clock processors are provided to economically control system and data clocks in high-speed signal converters. The processors generally include at least one of a delay-locked loop, phase-locked loop or a duty cycle stabilizer which generates an error signal in its operation. In the example of a stabilizer, it is configured to respond to an input clock to initiate a first portion of each cycle of the system clock and to include a control loop to provide an error signal that controls a second portion of the cycle to thereby maintain a selected duty cycle. The processors also include a data clock aligner configured to share the error signal and provide a data clock that is delayed by a selected delay from a selected one of the input and system clocks. In addition to providing effective control that is independent of disturbing effects (e.g., temperature and clock rate), the shared use reduces processor costs.

Abstract: A high-voltage, low-leakage, bidirectional electrostatic discharge (ESD, or other electrical overstress) protection device includes a doped well disposed between the terminal regions and the substrate. The device includes an embedded diode for conducting current in one direction, and a transistor feedback circuit for conducting current in the other direction. Variations in the dimensions and doping of the doped well, as well as external passive reference via resistor connections, allow the circuit designer to flexibly adjust the operating characteristics of the device, such as trigger voltage and turn-on speed, to suit the required mixed-signal operating conditions.

Abstract: Embodiments of the present invention provide a monitoring system that may include a plurality of monitors. Each may have a plurality of input pairs coupled to respective components of a component stack, wherein adjacent monitors each have an input pair coupled to a common component. Embodiments of the present invention provide an integrated circuit that may include a plurality of detectors to locally measure a first group of channels. The integrated circuit may also include a receiver operable to receive a measurement of at least one channel of the first group of channels, and a controller to calculate a correction factor based on the received measurement and a local measurement of the at least one channel and to correct all first group measurements with the correction factor.

Abstract: A method of producing an integrated MEMS resonator includes providing a substrate including single crystal silicon and partially forming a resonator in a first portion of the substrate, the resonator having a resonating element formed by the substrate and an electrode, the resonating element and the electrode forming a variable capacitor. The method also includes forming circuitry in a second portion of the substrate, the circuitry configured for detecting capacitance of the variable capacitor and finish forming the resonator and integrating the resonator with the circuitry so that the electrode is in communication with the circuitry.

Abstract: In various embodiments, the invention relates to bond pad structures including planar transistor structures operable as over-voltage clamps.

Abstract: A battery monitor for monitoring the performance of at least one battery within an array of batteries, comprising: a data acquisition device for measuring at least one parameter of the at least one battery associated with the battery monitor, a first data interface operable to exchange data with a first device, and a second data interface operable to exchange data with a second device.

Abstract: A thin silicon-rich nitride film (e.g., having a thickness in the range of around 100A to 10000A) deposited using low-pressure chemical vapor deposition (LPCVD) is used for etch stop during vapor HF etching in various MEMS wafer fabrication processes and devices. The LPCVD silicon-rich nitride film may replace, or be used in combination with, a LPCVD stoichiometric nitride layer in many existing MEMS fabrication processes and devices. The LPCVD silicon-rich nitride film is deposited at high temperatures (e.g., typically around 650-900 degrees C.). Such a LPCVD silicon-rich nitride film generally has enhanced etch selectivity to vapor HF and other harsh chemical environments compared to stoichiometric silicon nitride and therefore a thinner layer typically can be used as an embedded etch stop layer in various MEMS wafer fabrication processes and devices and particularly for vapor HF etching processes, saving time and money in the fabrication process.