Abstract: A circuit is provided which is adapted to compensate for the inherent parasitic capacitance which is implicit in switched capacitor circuits. By shielding the parasitic capacitance to a common node of the circuit and then connecting this shield to a voltage source that tracks the voltage change at the input to an amplifier, the present invention provides a bootstrapping effect that enables a minimization of the effect of the parasitic capacitance. The invention also provides a circuit that is adapted to compensate for curvature in the output of a switched capacitor bandgap reference.

Abstract: A switched current temperature sensing circuit (1) comprises a measuring transistor (Q1) which is located remotely of a measuring circuit (5) which applies three excitation currents (I1,I2,I3) of different values to the measuring transistor (Q1) in a predetermined current sequence along lines (10,11). Resulting base/emitter voltages from the measuring transistor (Q1) are applied to the measuring circuit (5) along the same two lines (10,11) as the excitation currents are applied to the measuring transistor (Q1). Voltage differences ?Vbe of successive base/emitter voltages resulting from the excitation currents are integrated in an integrating circuit (36) of the measuring circuit (5) to provide an output voltage indicative of the temperature of the measuring transistor (Q1).

Abstract: A novel circuit is used to monitor the common-mode voltage at the summing junctions of the first integrator in a continuous-time ?? ADC, wherein the circuit produces a control voltage which adjusts the quiescent current of the feedback DAC to compensate for any common-mode offset current. Since the adjustment takes place within the feedback DAC, there is no extra noise added to the differential signal path. The implementation provides for no degradation to the SNR of the converter.

Abstract: A charge pump circuit is disclosed that includes a positive current output circuit for providing a positive current to an output of the charge pump circuit, a negative current output circuit for providing a negative current to the output of the charge pump circuit, and a calibration unit for permitting the charge pump circuit to be adjusted to reduce any current mismatch between the positive and negative currents and to provide that any current mismatch is integrated into a PLL loop filter capacitance.

Abstract: An indirect variable frequency synthesiser for synthesising selectable frequencies from a reference frequency including a multi-divisor programmable frequency divider located in a feedback loop of the frequency synthesiser for dividing the feedback frequency in the feedback loop, the divider being responsive to a varying control signal applied thereto representative of a rational number of selectable value for selecting the divisor thereof for fractional division of the feedback frequency. A variable modulus interpolator converts a fractional part of the rational number of selectable value to a varying digital code representative of the fractional part of the rational number.

Abstract: Methods and apparatus for accessing flash memory in a continued burst mode are provided. The apparatus includes a processor for executing instructions including memory access instructions, the processor generating a next access signal that indicates if a next memory access is in sequence with a current memory access, a memory having a continued burst mode of operation, and a bus interface for controlling access to the memory in response to the memory access instructions. The bus interface unit enables the continued burst mode of the memory while the next access signal is asserted.

Abstract: A method for monitoring the performance of a test apparatus (1) for testing a batch of integrated circuits. The apparatus 1 comprises a test site 2 in which the integrated circuits are sequentially tested, and a microprocessor (4) for carrying out the appropriate tests on the integrated circuits. A first ROM (5) stores a computer programme for controlling the operation of the microprocessor (4) for carrying out the tests, and a first RAM (10) stores a computer programme for controlling the operation of the microprocessor (4) for monitoring the performance of the test apparatus (1). In particular, the computer programme stored in the first RAM (10) operates the microprocessor (4) for computing the test time period for each integrated circuit tested, and also for computing the intervening time periods between each integrated circuit tested. The intervening time periods between the respective test time periods are classified as either first or second category delays or index time periods.

Abstract: An RMS-to-DC converter implements the difference of squares function using two squaring cells operating in opposition to attain a balance. Each of the squaring cells is implemented as a grounded-base transistor and a two-transistor current mirror. The emitter of the grounded-base transistor is coupled to the input terminal of the current mirror at a node which receives the input signal. The collector of the grounded-base transistor and the output of current mirror are coupled together to generate an output current having a square-law relationship to the input signal. One of the squaring cells receives the input signal and operates at high frequencies (HF), while the other receives a feedback signal and operates in a quasi-DC mode. In a measurement node, a nulling circuit closes a feedback loop around the DC squaring cell to null the output currents from the squaring cells.

Abstract: A transceiver system is disclosed for use in a telecommunication system. The transceiver system includes a transmission circuit including a differential transmitter input coupled to a differential input of a transmission amplifier, a receiver circuit including a differential receiver output coupled to a differential output of a receiver amplifier, and a transmission line interface circuit that is coupled to a differential output of the transmission amplifier and to a differential input of the receiver amplifier. The transmission line interface circuit providing a second order high pass transfer function.

Abstract: A circuit and method are provided to enable the synchronization of an on-demand, synchronous signal with an asynchronous signal. The synchronous signal is activate only for a portion of the period of the asynchronous signal, thus providing beneficial power conservation. The synchronous signal is activated in response to a first edge of the asynchronous signal, and deactivated in response to a second edge of the asynchronous signal.

Abstract: A novel optical path switching system, architecture and technique wherein light beam data traffic is to be switched by MEMS mirrors between source and destination nodes, and test ports are used to set up optical paths even before the real data traffic is propagated, with a combination of an electrical mirror-sensing feedback loop for controlling coarse mirror positioning, and an optical path power-sensing feedback loop for controlling fine adjustments in the mirror position.

Abstract: A center focussed SIMD array system including an SIMD array including a plurality of processing elements arranged in a number of columns and rows and having two mutually perpendicular axes of symmetry defining four quadrants; and a sequencer circuit for moving the data in each element to the next adjacent element towards one axis of symmetry until the data is in the elements along the one axis of symmetry and then moving the data in the elements along the the one axis of symmetry to the next adjacent element towards the other axis of symmetry until the data is at the four central elements at the origin of the axes of symmetry.

Abstract: A first device comprises a loop circuit to control a sample rate of a digital circuit element. A circuit comprises a digital loop circuit to control a sample rate of a digital circuit element to be a function of a frequency of a signal received by the circuit. A second device receives two or more sampled data streams having sample rates different from one another, converts the sample rate of one or more of the data streams to provide two or more data streams having sample rates compatible with one another, and combines the two data streams. Sample rate converter devices are used in a PLL and a clock recovery circuit.

Abstract: Signal converters are provided that accurately process dc-coupled source signals in the presence of different predetermined voltage and current source requirements. Processing structures are described that satisfy these requirements while providing accurate control of common mode levels along a processing path and accurate reduction of converter offset errors.

Abstract: A temperature sensor circuit is provided which is adapted to provide an indication of the temperature on a chip. The sensor includes a bandgap temperature sensor which is sequentially driven by a plurality of current sources. The current sources are shuffled so as to minimize problems associated with matching currents.

Abstract: A read-write interface system and method for a peripheral device includes storing data to be processed by a peripheral device; receiving a set of input data bits; transferring the set of input data bits from the shift register to the latch circuit in a write operation; accessing a leading bit of the set of input data bits from the latch circuit in advance of a read operation; and enabling in a read operation the rest of the input data bits in the latch circuit to be transferred to the shift register to be output with the leading bit.

Abstract: A switched capacitor buffer operating by the push-pull method is taught. The buffer may include a pull-up device and a pull-down device. A switched capacitor circuit may be used to control the pull-up device and the pull-down device to achieve accurate push-pull operation. According to some embodiments, the switched capacitor buffer displays an optimal combination of design simplicity, low power consumption and high-frequency response.

Abstract: A system and apparatus for testing a micromachined optical device includes a computerized test station that generates signals to control the micromachined optical device as well as various test equipment and analyzes signals generated by the micromachined optical device and various test equipment. The computerized test station typically provides for both manual and automated testing of the micromachined optical device. In order to test the micromachined optical device, various optical measurement devices are typically mounted on a frame. The frame is configured so as to maintain proper alignment between the optical measurement devices and the micromachined device under test. The frame is mounted to or integral with a focusing device. The frame moves along with focusing movements of the focusing device in such a way that the optical measurement devices are properly aligned with the micromachined device under test when the focusing device is focused on the micromachined device under test.

Abstract: Bias controllers are provided which alter a bias control signal so that a bias signal (e.g., a current signal) of an electronic network rapidly responds to increases in the rate-of-change of the network's analog input signal. This enhances the linearity of a system that includes the electronic network. Subsequent decreases in the rate-of-change are sensed and a decrease of the bias control signal is then paced at a rate selected to ignore short-term rate-of-change variations (e.g., modulation variations) but follow longer-term rate-of-change reductions to thereby enhance system efficiency without sacrificing system linearity.

Abstract: In parallel with accesses to a cache made by a core processor, a DMA controller is used to pre-load data from a main memory into the cache. In this manner, the pre-load function can make the data available to the processor application before the application references the data, thereby potentially providing a 100% cache hit ratio since the correct data is pre-loaded into the cache. In addition, if a copy-back cache is employed, the cache memory system can also be configured such that processed data can be dynamically unloaded from the cache to the main memory in parallel with accesses to the cache made by the core processor. The pre-loading and/or post unloading of data may be accomplished, for example, by using a DMA controller to burst data into and out of the cache in parallel with accesses to the cache by the core processor. This DMA control function may be integrated into the existing cache control logic so as to reduce the complexity of the cache hardware (e.g.