Abstract: A wideband impedance attenuator includes a phase-locked loop filter, a voltage-controlled oscillator connected to the phase-locked loop filter during transmit, and an impedance circuit connected to the phase-locked loop filter and the voltage controlled oscillator. The impedance circuit is a scaled version of the phase-locked loop filter. Moreover, the wideband impedance attenuator attenuates a Gaussian frequency shift key modulation signal by a factor of 1/(N+1) using the impedance circuit, which has an impedance of N*Z(s), and the phase-locked loop filter, which has an impedance of Z(s). An output frequency is generated using a voltage-controlled oscillator wherein the output frequency corresponds to the attenuated Gaussian frequency shift key modulation signal. In addition, a comparator compares a voltage of an output from the programmable gain amplifier with a voltage necessary to produce a predetermined frequency shift in a voltage-controlled oscillator to produce a gain signal.

Abstract: A flip-bonding technique is used to fabricate complex micro-electromechanical systems. Various micromachined structures are fabricated on the front side of each of two wafers. One of the wafers is flipped over and bonded to the other wafer so that the front sides of the two wafers are bonded together in a flip-stacked configuration.

Abstract: A method of forming a MEMS device produces a device layer wafer having a pre-formed conductive pathway before coupling it with a handle wafer. To that end, the method produces the noted device layer wafer by 1) providing a material layer, 2) coupling a conductor to the material layer, and 3) forming at least two conductive paths through at least a portion of the material layer to the conductor. The method then provides the noted handle wafer, and couples the device layer wafer to the handle wafer. The wafers are coupled so that the conductor is contained between the material layer and the handle wafer.

Abstract: A bipolar differential input stage with an input bias current cancellation circuit comprises an input pair and a bipolar tracking transistor. The input stage is arranged such that the collector currents in the input pair and tracking transistor, and the collector-emitter voltages of the input pair and tracking transistor, are substantially equal. A lateral PNP transistor's first collector provides the tracking transistor base current required to achieve the substantially equal collector current, and second and third collectors provide copies of the tracking transistor base current as bias current cancellation currents to the bases of the input pair, thereby reducing the input stages' input bias currents.

Abstract: One embodiment of the invention is directed to a method comprising an act of performing digital correction of an offset in a system comprising an analog-to-digital converter (ADC) having a usable input range that is greater than a nominal input range, wherein the offset exists at an input of the ADC. Another embodiment of the invention is directed to a system comprising an ADC having a usable input range that is greater than a nominal input range, wherein an offset exists at an input of the ADC and the offset is corrected using digital correction.

Abstract: A translinear amplifier is disclosed. A loop amplifier drives the bases of the input and output transistor pairs from the differential collector voltage of the input pair. The loop amplifier contains a third differential pair (a gain pair). The tail current of the gain pair is inversely related to the tail current of the input pair, such that loop amplifier gain remains stable when the transconductance of the input pair changes (due, e.g., to input gain changes). In one embodiment, a linear-in-dB interface is provided that adjusts input pair tail current exponentially (and gain pair tail current exponentially and inversely) to linear voltage changes at a gain input.

Abstract: A common mode linearized input stage comprises NPN and PNP differential pairs biased with respective tail currents at respective common emitter nodes, with each pair connected to receive a differential input signal. A tail current modulation circuit generates complementary output currents as a function of the voltage difference between the common emitter nodes, and first and second tail current sources generate the tail currents as a function of the complementary output currents. The tail current modulation circuit and the first and second tail current sources are arranged such that the magnitudes of the tail currents increase with an increasing differential input signal.

Abstract: A memory system for operation with a processor, such as a digital signal processor, includes a high speed pipelined memory, a store buffer for holding store access requests from the processor, a load buffer for holding load access requests from the processor, and a memory control unit for processing access requests from the processor, from the store buffer and from the load buffer. The memory control unit may include prioritization logic for selecting access requests in accordance with a priority scheme and bank conflict logic for detecting and handling conflicts between access requests. The pipelined memory may be configured to output two load results per clock cycle at very high speed.

Abstract: An improved pipelined analog to digital converter that facilitates calibration for non-linearity errors and a method for obtaining calibration values. The analog to digital converter has a calibration mode in which the output bits for stages in the pipeline can be coupled to output pins of the device. Device pins that are used in normal operating mode to output the most significant bits of the ADC output are used in calibration mode to make available output bits of a pipeline stage being calibrated. A calibration method takes advantage of the outputs of the stages being directly observable to compute calibration values. The output bits of a pipeline stage are monitored as the analog input to the ADC is increased. A change in these bits identifies a subrange boundary. Errors are measured for values immediately above and immediately below each subrange boundary and used to compute correction factors.

Abstract: A current integration circuit includes an operational amplifier having a capacitor connected between its output and inverting input which integrates an input current. To prevent the op amp's output from becoming saturated, a charge dumping circuit dumps a known charge of the opposite polarity to that stored on the capacitor to the op amp's inverting input, thus reducing the charge on the capacitor and preventing the op amp's output from becoming saturated. A charge dump is triggered whenever the op amp's output exceeds a predetermined trip voltage. Counting the number of charge dumps performed during a given integration period provides a coarse indication of the magnitude of the integrated input current, and the output of the op amp provides a fine indication.

Abstract: A digital blanking circuit allows a first digital input signal transition to be passed on to a following stage, but prohibits the passing of subsequent transitions for a predetermined blanking interval. One embodiment of the present invention employs rising edge and falling edge latches, the inputs of which receive the digital input signal and the outputs of which are connected to a two-to-one multiplexer. The mux output is connected to a blanking interval circuit, which is triggered to begin timing a blanking interval by a multiplexer output transition. The blanking interval circuit provides outputs which control the latches and selects the latch output to be transferred to the multiplexer output such that the multiplexer output is prevented from transitioning during a blanking interval.

Abstract: Methods and apparatus for reducing the thermal noise integrated on a storage element are disclosed. One embodiment of the invention is directed to a sampling circuit comprising a sampling capacitor to store a charge, the sampling capacitor being exposed to an ambient temperature. The sampling circuit further comprises circuitry to sample the charge onto the capacitor, wherein thermal noise is also sampled onto the capacitor, and wherein the circuitry is constructed such that the power of the thermal noise sampled onto the capacitor is less than the product of the ambient temperature and Boltzmann's constant divided by a capacitance of the sampling capacitor. Another embodiment of the invention is directed to a method of controlling thermal noise sampled onto a capacitor. The method comprises an act of independently controlling the spectral density of the thermal noise and/or the bandwidth of the thermal noise.

Abstract: Input and output sections of an analog-to-digital converter are joined by an interface. In the input section, an analog input signal is converted to a multi-bit digital signal before being converted, by a noise-shaping converter such as a sigma-delta modulator, to a lower bit signal. The lower bit signal is carried across the interface before being converted, by a digital filter to recover the original multi-bit signal. The same principle is applied to the input and output sections of a digital-to-analog converter.

Abstract: Computer-implemented techniques are provided for synthesizing sounds of an internal combustion engine vehicle using a physical model of the vehicle. In general terms, the method includes independently generating and/or synthesizing separate components of the vehicle sound, then combining these components to produce a final sound. Using a physical model of the vehicle, the separate components of the vehicle sound are independently generated from vehicle control parameters characterizing the operating conditions of the vehicle. The components are then combined using mixers and equalizers to produce a realistic vehicle sound. The present technique allows independent control of the separate components of the vehicle sound, is not limited to specific vehicles, and does not require recorded sounds taking large amounts of storage space.

Abstract: A universally accessible fully programmable memory built-in self-test (MBIST) system including an MBIST controller having an address generator configured to generate addresses for a memory under test, a sequencer circuit configured to deliver test data to selected addresses of the memory under test and reading out that test data, a comparator circuit configured to compare the test data read out of the memory under test to the test data delivered to the memory under test to identify a memory failure, and an externally accessible user programmable pattern register for providing a pattern of test data to the memory under test. The system includes an external pattern programming device configured to supply the pattern of test data to the user programmable data pattern register.

Abstract: A switched noise filter circuit for DC-DC converters which use the instantaneous output voltage to establish the converter's duty ratio. The converter cycles the switching element on and off for time intervals Ton and Toff, respectively. A switching control circuit includes a filter capacitance connected between the feedback node and ground, and a comparator which compares a feedback voltage Vfb with a fixed voltage Vref; at least one of Ton and Toff is a “modulated” interval which is terminated when Vfb crosses Vref due to the discharge of the filter capacitance. A switched noise filter circuit applies an offset voltage to Vfb during at least one of Ton, and Toff, with the offset voltage disconnected from Vfb by the beginning of the modulated interval or shortly thereafter. When the offset voltage is properly applied, the effect of extraneous electromagnetic noise coupled into Vfb is reduced.

Abstract: An electronic device, such as a microprocessor, with a timing circuit. The timing circuit contains a phase locked loop that, during a first interval, checks whether a control signal in the phase locked loop is between a maximum allowed value and a minimum allowed value. When the control signal in the phase locked loop is above a maximum allowed value or below a minimum allowed value, the control circuit disables the phase locked loop for a second interval. When the control signal in the phase locked loop is below a maximum allowed value and above a minimum allowed value, the timing circuit indicates that the output of the phase locked loop is stable.

Abstract: A memory is provided in which each memory cell can be in a first state or a second state, and those cells which should be in the first state always correctly power up into that state whereas cells which should be in the second state may power up incorrectly. A counting arrangement is provided to count the number of cells in either of the states and to compare this with a predetermined number. If the numbers do not match, a memory reset is performed. The memory cells can be constructed from a single fusible element thereby saving space whilst also consuming substantially zero power following power up.

Abstract: A high side current monitor circuit includes an op amp which is coupled across a sensing element which carries a current Isense and develops a shunt voltage Vsense. A feedback transistor driven by the op amp output conducts an output current Iout through a resistor to a current output node necessary to make the op amp inputs equal, such that Iout is proportional to Isense. Iout is conducted through a resistor to generate a ground-referred voltage proportional to Vsense. When the common mode voltage of Vsense is greater than the op amp's breakdown voltage, a discrete transistor is connected between the current output node and ground to stand off the voltage across the amp. The monitor circuit is arranged such that it can be powered with a limited fraction of the common mode voltage when used with a discrete transistor, and is self-biased when used without a discrete transistor.

Abstract: A metallization stack is provided for use as a contact structure in an integrated MEMS device. The metallization stack comprises a titanium-tungsten adhesion and barrier layer formed with a platinum layer formed on top. The platinum feature is formed by sputter etching the platinum in argon, followed by a wet etch in aqua regia using an oxide hardmask. Alternatively, the titanium-tungsten and platinum layers are deposited sequentially and patterned by a single plasma etch process with a photoresist mask.