Abstract: A semiconductor substrate (1) comprising an SOI (2) formed therein. The semiconductor substrate (1) comprises first and second wafers (4,6) which are directly bonded together along a bond interface (9). Prior to bonding the wafers (4,6), a portion (15) of the second wafer (6) is ion implanted to form a p+ region for facilitating selective etching thereof to form a buried cavity (16), in which a buried insulating layer is subsequently formed under a portion (10) of the first wafer (4) for forming the SOI (2). After bonding of the first and second wafers (4,6) a communicating opening (20) is etched through the first wafer (4) to the bond interface (9), and the selectively etchable portion (15) is etched through the communicating opening (20) to form the buried cavity (16). The buried cavity (16) is then filled with deposited oxide to form the buried insulating layer (11).

Abstract: Methods and apparatus are provided for clock domain conversion in digital processing systems. The methods include operating a first circuit in a fast clock domain with a fast clock and operating a second circuit in a slow clock domain with a slow clock. To transfer signals from the fast clock domain to the slow clock domain, a first synchronization signal is asserted during each fast clock cycle in which a slow clock edge occurs. A fast signal is transferred from the fast clock domain to the slow clock domain on a fast clock edge when the first synchronization signal is asserted. To transfer signals from the slow clock domain to the fast clock domain, a second synchronization signal is asserted during each fast clock cycle that immediately follows a slow clock edge. A slow signal is transferred from the slow clock domain to the fast clock domain on a fast clock edge when the second synchronization signal is asserted.

Abstract: The present invention is directed to an echo canceller adapted for use in a communication system that includes a hybrid circuit. The echo canceller comprises an adaptive digital filter that generates an estimated echo signal {circumflex over (z)}[k] in response to: (i) a sampled input data sequence x[k] and (ii) an error signal sequence e[k] indicative of the difference between a near end signal sequence y[k] and the estimated echo signal {circumflex over (z)}[k]. The adaptive digital filter computes filter coefficients based upon the error signal sequence e[k] using a stochastic quadratic descent estimator, such as for example a least mean square (LMS) estimator, that employs a dynamically adjustable step size vector ?[k].

Abstract: A clock enable system for a multichip device includes a first integrated circuit including a clock signal and at least a second integrated circuit including at least one functional block periodically requiring clock signals from the first integrated circuit; a clock required circuit responsive to each functional block for providing a clock required signal in response to activation of any one or more of the functional blocks; and a clock enable circuit responsive to the clock required signal for enabling the first integrated circuit to provide clock signals to the functional blocks on the second integrated circuit.

Abstract: A method and a processor for processing two digital video signals clocked by respective clock signals of identical frequency but with a constant phase shift therebetween. Standard definition and progressive scan digital video signals which are clocked at first and second clock signals CLOCK—1 and CLOCK—2, respectively, of identical frequency with a constant phase shift therebetween are interfaced with a processing circuit (7) by an interface circuit (10). The progressive scan signal is clocked into a first register (20) on the second clock signal CLOCK—2, and is clocked to a second register (21) by the first clock signal CLOCK—1 and in turn to a third register (22) by the first clock signal CLOCK—1. The edge of the first clock signal CLOCK—1 on which the progressive scan signal is clocked into the second register (21) is chosen to allow sufficient time to clock the signal.

Abstract: A packaged microchip has a stress sensitive microchip, a package having a package modulus of elasticity, and an isolator between the microchip and the package. The isolator has an isolator modulus of elasticity that has a relationship with the package modulus of elasticity. This relationship causes no more than a negligible thermal stress to be transmitted to the microchip.

Abstract: A wafer cap protects micro electromechanical system (“MEMS”) structures during a dicing of a MEMS wafer to produce individual MEMS dies. A MEMS wafer is prepared having a plurality of MEMS structure sites thereon. Upon the MEMS wafer, the wafer cap is mounted to produce a laminated MEMS wafer. The wafer cap is recessed in areas corresponding to locations of the MEMS structure sites on the MEMS wafer. The capped MEMS wafer can be diced into a plurality of MEMS dies without causing damage to or contaminating the MEMS die.

Abstract: A wafer cap protects micro electromechanical system (“MEMS”) structures during a dicing of a MEMS wafer to produce individual MEMS dies. A MEMS wafer is prepared having a plurality of MEMS structure sites thereon. Upon the MEMS wafer, the wafer cap is mounted to produce a laminated MEMS wafer. The wafer cap is recessed in areas corresponding to locations of the MEMS structure sites on the MEMS wafer. The capped MEMS wafer can be diced into a plurality of MEMS dies without causing damage to or contaminating the MEMS die.

Abstract: In one embodiment, a programmable processor searches an array of N data elements in response to N/M machine instructions, where the processor has a pipeline configured to process M data elements in parallel. In response to the machine instructions, a control unit directs the pipeline to retrieve M data elements from the array of elements in a single fetch cycle, concurrently compare the data elements to M current extreme values, and update the current extreme values, as well as M references to the current extreme values, based on the comparisons.

Abstract: A bond pad structure for an integrated circuit includes first and second active devices formed in a substrate, first and second buses above the first and second active devices, respectively, a bond pad above the first and second buses, first interconnections between the first and second active devices and the bond pad, and second interconnections between the first and second active devices and the first and second buses, respectively. The first active device may be at least one PMOS transistor, and the second active device may be at least one NMOS transistor. A guard band region may be formed in the substrate.

Abstract: A dual voltage switch enables the generation of a pulse which toggles between user-provided first and second voltages (V1 and V2), for which the positive and/or negative slew rates are programmable by means of a user-provided capacitance. A first switch conducts a current I1 between V1 and a common output node in response to a first control voltage, and a second switch conducts a current I2 between V2 and the common output node in response to a second control voltage. A capacitance C is connected to the common output node. A control circuit alternately provides the first and second control voltages such that the common output node is pulled up to V1 at a transfer rate of I1/C when the first control voltage is provided, and pulled down to V2 at a transfer rate of ?I2/C when the second control voltage is provided.

Abstract: A multiple-phase DC—DC converter adds at least one additional phase to an N-phase DC—DC converter to improve the converter's response to changes in load. In one embodiment, an additional phase operates at a switching frequency greater than that of the N phases, to generate a current which is added to the N phase currents to improve the converter's response to changes in load. In another embodiment, an additional phase is configured to improve the converter's response to a load release. Here, the additional phase is kept off during load increase and steady-state conditions. However, when a load release occurs, the additional phase is turned on and acts to extract current from the converter's output terminal while the N phase currents slowly fall, to reduce the magnitude of output voltage overshoot that occurs on load release.

Abstract: Simple, inexpensive, lightweight secondary display systems are provided which extract video data and a direct coupled (DC) voltage from the CardBus slot of a computer. The video data is converted to a video display signal in a video controller and preferably coupled to a head-wearable display (HWD) over an optical fiber. The HWD is powered by the DC voltage which is coupled to it by a metallic conductor bundled with the optical fiber.

Abstract: A single instruction multiple data (SIMD) array cell for processing a data stream, the array including a plurality of cells, each cell having a memory circuit for storing a predetermined region of the data stream; a location register circuit for representing the size and location of the predetermined region of the data stream; a unique identification number; and an arithmetic logic unit responsive to the identification number and a single command common to all cells in a load mode to compute a unique start position for its cell for receiving the predetermined region of the direct memory access data stream. In an execution mode the command word includes an address field applicable to all cells, a data field and an instruction to be performed by the arithmetic logic unit. The arithmetic logic unit in each cell performs the instruction directly on the local value at that address in its memory with the data in the data field.

Abstract: A drive circuit for a brushless DC motor includes a switch constructed and arranged to drive the motor with a pulse signal responsive to a control signal, and control circuitry coupled to the switch and constructed and arranged to generate the control signal responsive to rotor position information from the motor so as to synchronize the pulse signal to the rotor position. A current sensing device can be used to provide the rotor position information to the control circuitry by sensing current flowing through the motor.

Abstract: In an optical switching apparatus having a mirror structure bonded to a substrate, the gap between the mirror structure and the substrate is controlled by mechanical standoffs placed between the mirror structure and the substrate. The mirror structure is bonded to the substrate using solder. The mechanical standoffs are formed from a material having a higher melting point than that of the solder. The mirror structure is bonded to the substrate under pressure at a temperature between the melting point of the solder and the melting point of the mechanical standoffs.

Abstract: A highly-programmable Finite Impulse Response (FIR) digital filter overcomes the limitations of conventional configurations. Specifically, a compound FIR filter configuration is provided, offering the advantages of heightened programmability in both transfer function coefficients hf, hg and in degree of interpolation; distribution and sharing of resources between F and G filter portions, mode-switching capability between high-pass and low-pass modes, and programmable truncation/saturation.

Abstract: A programmable input voltage range analog-to-digital converter in which a split gate oxide process allows the use of high voltage (±15 volt) switches on the same silicon substrate as standard sub-micron 5 volt CMOS devices. With this process, the analog input voltage can be sampled directly onto one or more sampling capacitors without the need for prior attenuation circuits. By only sampling on a given ratio of the sampling capacitors, the analog input can be scaled or attenuated to suit the dynamic range of a subsequent ADC. In the system of the present invention, the sampling capacitor can be the actual capacitive redistribution digital-to-analog converter (CapDAC) used in a SAR ADC itself, or a separate capacitor array. By selecting which bits of the CapDAC or separate sampling array to sample on, one can program the input range.

Abstract: A circuit (1) comprising eight DACs (2a to 2h), the analog outputs of which are applied to the non-inverting inputs (6) of corresponding op-amps (7a to 7h) for gaining up the analog output voltage from the corresponding DAC (2). The op-amps (7) are identical, and are configured in a non-inverting mode with a closed loop gain of two provided by first and second resistors (R1) and (R2). Primary outputs (8) of the op-amps (7) are coupled to output pins (9a to 9h) of the circuit (1). The second resistors (R2) couple primary inverting inputs (12) of the op-amps (7) to a common lo voltage reference rail (14), which is coupled to a true ground reference pin (15) through a coupling wire (16)which exhibit a combined inherent resistance (Rp). The voltage reference on the common voltage reference rail (14) varies with time as the output signals of the pa-amps (7) vary, and would thus result in cross-talk between the DACs (2a to 2h).

Abstract: A MEMS device has at least one conductive path extending from the top facing side of its substrate (having MEMS structure) to the bottom side of the noted substrate. The at least one conductive path extends through the substrate as noted to electrically connect the bottom facing side with the MEMS structure.