Patents Assigned to Analog Devices, Inc.
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Publication number: 20030078013Abstract: A wireless terminal circuit includes a variable high frequency clock oscillator that provides a high frequency clock signal and a fixed low frequency clock oscillator that provides a low frequency clock signal. A phase-locked loop adjusts a ratio of the frequency of the high frequency clock signal to the low frequency clock signal by adjusting the frequency of the high frequency clock signal. The phase locked loop includes a divider for dividing the high frequency clock signal, the divide ratio of which divider is controlled by a sigma-delta modulator. A wireless terminal local oscillator calibration circuit includes a frequency control circuit including both the high frequency clock oscillator and the low frequency clock oscillator.Type: ApplicationFiled: September 17, 2002Publication date: April 24, 2003Applicant: Analog Devices, Inc.Inventor: Paul F. Ferguson
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Patent number: 6552404Abstract: Electro-mechanical structures and methods for forming same are disclosed. The structures are integratable onto an integrated circuit. The structures have a deformeable element formed in a plane substantially perpendicular to the substrate of the integrated circuit.Type: GrantFiled: April 17, 2001Date of Patent: April 22, 2003Assignee: Analog Devices, Inc.Inventors: Eamon Hynes, John Wynne
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Patent number: 6552577Abstract: A logic buffer includes a logic gate having at least two input terminals and two output nodes, a plurality of output terminals, each having a capacitance associated therewith and a pull-up circuit interconnected between each output node and the plurality of output terminals for alternately charging the capacitance of each output terminal. The buffer also includes a differential pull-down circuit including a common pull-down current source, the pull-down device interconnected between the output nodes and the output terminals for inversely alternately discharging the capacitances through the common pull-down current source for accelerating the discharge of the capacitance of the respective output terminal.Type: GrantFiled: February 16, 2000Date of Patent: April 22, 2003Assignee: Analog Devices, Inc.Inventor: Kimo Y. F. Tam
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Patent number: 6549070Abstract: A high gain amplifier includes an intermediate gain stage; an output gain stage driven by the intermediate gain stage; an input stage, for driving the intermediate gain stage, which is balanced between positive and negative feedback in normal operation; bias means for driving the input stage to maintain balance between positive and negative feedback in normal operation; and a resistance for limiting the output current of the intermediate stage in response to the input stage being overdriven into positive feedback.Type: GrantFiled: August 21, 2000Date of Patent: April 15, 2003Assignee: Analog Devices, Inc.Inventors: Chau C. Tran, Adrian Paul Brokaw
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Patent number: 6549053Abstract: An adjustable offset voltage circuit is disclosed for applying an offset voltage to a differential voltage in a digital data receiver system. The circuit includes a pair of emitter follower units, and a pair of current generating units. The first emitter follower unit provides a first offset voltage, and the second emitter follower unit provides a second offset voltage. The first current generating unit provides a biasing current to the first emitter follower unit, and the second current generating unit provides a biasing current to the second emitter follower unit. The circuit also includes a pair of differential signal input ports, each of which is coupled to one of the first and second emitter follower units, and an offset adjustment unit for permitting offset adjustment of a differential output signal with respect to a differential input signal at the input ports.Type: GrantFiled: July 26, 2001Date of Patent: April 15, 2003Assignee: Analog Devices, Inc.Inventors: Eric M. J. Evans, Lawrence M. DeVito
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Patent number: 6549079Abstract: Feedback control loop systems are provided that enhance output-signal switching times without degrading other loop performance parameters. The systems reduce “kick-back” voltages that are generated in a loop filter by drive currents which rapidly drive a control loop oscillator to a loop acquisition range. This reduction reduces a frequency step in the oscillator output signal which would otherwise have to be driven to eliminate the frequency step with a consequent increase in the output-signal switching time. Structures are provided that reduce the kick-back voltage to thereby enhance output-signal switching times.Type: GrantFiled: November 9, 2001Date of Patent: April 15, 2003Assignee: Analog Devices, Inc.Inventor: David T. Crook
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Patent number: 6549057Abstract: An RMS-to-DC converter implements the difference-of-squares function by utilizing two identical squaring cells operating in opposition to generate two signals. An error amplifier nulls the difference between the signals. When used in a measurement mode, one of the squaring cells receives the signal to be measured, and the output of the error amplifier, which provides a measure of the RMS value of the input signal, is connected to the input of the second squaring cell, thereby closing the feedback loop around the second squaring cell. When used in a control mode, a set-point signal is applied to the second squaring cell, and the output of the error amplifier is used to control a variable-gain device such as a power amplifier which provides the input to the first squaring cell, thereby closing the feedback loop around the first squaring cell.Type: GrantFiled: October 23, 2000Date of Patent: April 15, 2003Assignee: Analog Devices, Inc.Inventor: Barrie Gilbert
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Patent number: 6545534Abstract: A differential variable gain amplifier (VGA) with constant input impedance and an adjustable one-pole filtering characteristic is provided. Each input of the VGA has a set of parallel resistors connected thereto. Except for one resistor in each set, each of the resistors of the two sets is connected to its corresponding summing junction (op-amp input), or to a corresponding resistor of the other set via a switch. Switching the resistors to their corresponding summing junction or to the corresponding resistor of the other set provides for the variable gain function, where the gain is proportional to the number of resistors connected to the summing junction. The configuration of resistors provides a constant input impedance to the VGA of R/(n+1), where R is the resistance value of the resistors.Type: GrantFiled: February 13, 2001Date of Patent: April 8, 2003Assignee: Analog Devices, Inc.Inventor: Iuri Mehr
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Patent number: 6542042Abstract: A crystal oscillator circuit is disclosed including a differential amplifier, a positive feedback assembly, and a series resonant crystal assembly. The differential amplifier includes a first transistor and a second transistor. The positive feedback assembly is coupled to each of the first and second transistors, and has a loop gain of greater than unity. The series resonant crystal assembly is coupled to one of the first and second transistors, and includes a crystal and a capacitor.Type: GrantFiled: February 20, 2001Date of Patent: April 1, 2003Assignee: Analog Devices, Inc.Inventor: Simon Atkinson
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Patent number: 6542540Abstract: An adaptive equalizer provides different degrees of high frequency boosts to the received signal, while retaining a relatively constant phase shift for each boost setting. The response of the equalizer is controlled by a control circuit (e.g., a digital signal processor) to compensate for the high frequency signal attenuation primarily caused by the signal path. For example, the signal path may include a telephone line between the communications system (e.g., a modem) and the central office. The dynamic response of the equalizer is selected based upon the characteristics of the signal path which the receive signal travels along. The equalizer may receive single ended or doubled ended signals. Advantageously, the equalizer conditions the received signal to ensure efficient utilization of the dynamic range of the ADC located in the receive circuit path. The equalizer is suitable for on-chip implementation, resulting in lower cost and power consumption.Type: GrantFiled: December 21, 1998Date of Patent: April 1, 2003Assignee: Analog Devices, Inc.Inventors: Vincent W. Leung, John M. Khoury, Reza Shariatdoust
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Patent number: 6542099Abstract: A method of equalizing total signal delay across a digital to analog interface includes constructing a plurality of unit digital to analog converter cells each having a clock input and a data input and an analog output; constructing an analog output network for summing the analog outputs for delivery to a termination which in combination with the analog output network defines a first predetermined time delay between the unit cells; constructing a clock input distribution network for propagating a clock input to each of the unit cells tapped along the clock input distribution network; and connecting a second termination to the clock input distribution network for establishing the clock input distribution network as a transmission line and defining in combination with the clock input distribution network a second predetermined time interval delay between the clock input to the unit cells equal to the first predetermined in the interval delay for synchronizing the propagation of the clock inputs propagating alonType: GrantFiled: November 21, 2001Date of Patent: April 1, 2003Assignee: Analog Devices, Inc.Inventors: William G. J. Schofield, Douglas A. Mercer
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Publication number: 20030061561Abstract: A method, apparatus and product for use in generating a remainder based code generates a plurality of preliminary remainder based codes in response to specified data, and synthesizing a remainder based code for the specified data, in response to the plurality of preliminary remainder based codes. In one embodiment, the plurality of preliminary remainder based codes includes at least two preliminary remainder based codes each generated in response to a respective portion of the specified data. In another embodiment, at least two preliminary remainder based codes are generated at least partially concurrently with one another.Type: ApplicationFiled: February 20, 2001Publication date: March 27, 2003Applicant: Analog Devices, Inc.Inventors: Rasekh Rifaat, Boris Lerner
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Publication number: 20030056589Abstract: A micromachined device has a body suspended over a substrate and movable in a plane relative to the substrate. The body has a perimeter portion, a first cross-piece portion extending from one part of the perimeter portion to another part of the perimeter portion to define at least first and second apertures, a first plurality of fingers extending along parallel axes from the perimeter portion into the first aperture, and a second plurality of fingers extending along parallel axes from the perimeter portion into the second aperture.Type: ApplicationFiled: November 14, 2002Publication date: March 27, 2003Applicant: Analog Devices, Inc.Inventors: John A. Geen, Donald W. Carow
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Patent number: 6539443Abstract: A first device and a second device may be coupled to a bus. The first and second devices drive signals on the bus to establish a bus speed for a given message and to arbitrate for bus access.Type: GrantFiled: November 17, 2000Date of Patent: March 25, 2003Assignees: Intel Corporation, Analog Devices, Inc.Inventors: Robert A. Dunstan, Dale Stolitzka
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Patent number: 6538233Abstract: A method for releasing a structure from contact with a substrate in a micromechanical device includes the step of irradiating the structure with energy having parameters selected to produce a thermal gradient normal to the surface of the structure which causes upward bowing and release of the structure from the substrate. Preferably, the structure is irradiated with laser energy and, more preferably, the structure is irradiated with pulsed laser energy. The temperature gradient creates a strain gradient, due to thermal expansion, which causes the structure to bow upwardly. Support elements react and hold the structure up after the thermal gradient has disappeared.Type: GrantFiled: November 6, 2001Date of Patent: March 25, 2003Assignee: Analog Devices, Inc.Inventors: W. David Lee, Paul A. Ruggerio
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Patent number: 6538583Abstract: A system for encoding and decoding information of a codeblock from a memory buffer that includes a context modeler that receives from the memory buffer the codeblock and divides the codeblock into a plurality of codesegments or decodes a codeblock worth of information from received compressed data. The codesegments includes a plurality of bits. The context modeler processes each of the codesegments individually by determining whether any of the bits need special coding information or decoding. The context modeler outputs coded bits associated with the bits that are coded with the special coding information and context information associated with the coded bits or outputs a codeblock worth of information to the memory buffer. An arithmetic coder receives the context information and coded bits and compresses the coded bits or receives compressed data and decompresses the compressed data to produce context information and coded bits.Type: GrantFiled: March 15, 2002Date of Patent: March 25, 2003Assignee: Analog Devices, Inc.Inventors: Phil Hallmark, Richard Greene
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Patent number: 6534340Abstract: A cover cap for semiconductor wafer devices is disclosed. According to the invention, a wafer of material that is at least one of photo-etchable or transparent is patterned and attached as a cover to a substrate including a number of semiconductor devices. Preferably, the cover wafer is made from a photo-etchable material so that portions of the cover wafer may be selectively sensitized and etched. In particular, one or more cover caps may be defined in the cover wafer such that each cover cap corresponds to a respective device on the device substrate. Once the cover wafer is attached to the device substrate to form an assembly, the assembly is diced into individual devices and the devices are packaged. The invention provides several advantages for a number of semiconductor device fabrication applications, including those relating to image sensors, and micro-machined devices such as MEMS.Type: GrantFiled: November 18, 1998Date of Patent: March 18, 2003Assignee: Analog Devices, Inc.Inventors: Maurice S. Karpman, Dipak Sengupta
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Patent number: 6530275Abstract: An accelerometer has a movable electrode between two fixed electrodes to form a differential capacitor. Drivers provide AC drive signals to the fixed electrodes. The movable electrode is coupled through reading circuitry to an output terminal. In response to a sensed acceleration, feedback is provided from the output terminal to one or both drivers to null any AC signal on the movable electrode and to keep the electrostatic forces between the movable electrode and each of the fixed electrodes equal.Type: GrantFiled: August 25, 2000Date of Patent: March 11, 2003Assignee: Analog Devices, Inc.Inventors: David C. Hollocher, John Memishian
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Patent number: 6531970Abstract: Methods and apparatus are provided for sample rate conversion in a system including two or more sample rate converters. The method includes the steps of providing an input clock and an output clock to each of the sample rate converters, measuring a sample rate ratio of the clocks in one of the sample rate converters, designated as a master, and controlling each of the sample rate converters with the sample rate ratio measured by the master. The measured sample rate ratio may be transmitted from the master to each of the other sample rate converters. This approach matches the group delays among the sample rate converters.Type: GrantFiled: June 7, 2001Date of Patent: March 11, 2003Assignee: Analog Devices, Inc.Inventors: Kevin J McLaughlin, Robert W. Adams
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Patent number: RE38083Abstract: A voltage mode digital-to-analog converter (DAC) with an output buffer operational amplifier is provided with a rail-to-rail output voltage capability by reducing the DAC's output voltage swing to a range that is within the amplifier's permissible input signal range, and connecting the amplifier in a multiplier configuration to produce a corresponding multiplication of its input signal. The DAC output reduction is preferably achieved by delivering an n-bit input digital signal to an n+m bit DAC, and holding the DAC's m most significant bits OFF. The m most significant bits are dummy bits that are impedance matched with the DAC, while the amplifier is an operational amplifier with a feedback circuit that is also impedance matched to the DAC.Type: GrantFiled: November 4, 1999Date of Patent: April 22, 2003Assignee: Analog Devices, Inc.Inventor: James J. Ashe