Abstract: A method of packaging an integrated circuit singulates a wafer to form an integrated circuit, positions the integrated circuit on a carrier, and passivates the integrated circuit after the positioning the integrated circuit on the carrier. At this point, the integrated circuit is secured to the carrier. The method also electrically connects the integrated circuit to a plurality of exposed conductors.

Abstract: A fractional-N synthesizer with programmable output phase including a phase locked loop having an output signal whose frequency is a fractional multiple of an input reference signal, the phase locked loop including a frequency divider. A synchronization circuit responsive to the input reference signal for generating synchronization pulses at integer multiples of M periods of the input reference signal. An interpolator is responsive to F and M, where F is the fractional value and M is the modulus, to provide to the frequency divider an output which is a fractional value equal to, on average, the input fraction. A phase adjustment circuit is responsive to the synchronization circuit for varying the phase of the output signal with respect to the input reference signal.

Abstract: A system and method transmits graphic data received at varying frequencies at a fixed data rate. The frequency dependent data and associated data clock signal are received and the frequency dependent data is converted to frequency independent data. A ratio of a number of data clock cycles to a number of reference clock cycles is determined and transmitted. The frequency independent data and header data are transmitted, at a fixed rate, to a receiver, the fixed rate being a frequency greater than the frequency of the associated data clock signal. The received the frequency independent data is converted to frequency dependent data based upon the received determined ratio. The communication channel may include an optical fiber and a tension member wherein control data is transmitted along the tension member and graphic data is transmitted along the optical fiber.

Abstract: A method for obtaining virtual path identifier, virtual channel identifier, and encapsulation values in an asynchronous transfer mode access device for a network using either non-static or static internet protocol address assignments and asynchronous transfer mode adaptation layer 5. In the non-static environment, a plurality of discovery packets are generated, but in the static environment, a plurality of address resolution protocol packets are generated. Headers are added to the plurality of packets, such that a first set of packets, each packet including a logical link control header, and a second set of packets, each packet including a virtual channel multiplexed header, are realized. The first and second sets of packets are encapsulated and then transmitted to a central office.

Abstract: A processing system supporting a secure mode of operation is disclosed. The processing system includes a read-only hardware key that is only accessible in secure mode.

Abstract: Display structures and methods are provided that introduce redundancy and use this redundancy with different mapping rules on different interleaved display lines to visually diffuse display artifacts. The artifacts are typically produced by errors in the transmission and recovery of analog display signals that subsequently drive digital displays. This visual diffusion substantially reduces the display artifacts and, because these visual improvements require only one element (an ADC) in the display system to be configured at a higher resolution, the visual advantageous are realized with relatively low cost.

Abstract: In one aspect, a method of reducing power consumption in a circuit by adaptive bias current generation of a bias current configured to bias, at least in part, at least one amplifier of the circuit is provided. The method comprises establishing the bias current based, at least in part, on a reference frequency of a reference clock providing a clock signal to at least one component of the circuit, and changing the bias current in response to a change in the reference frequency of the at least one reference clock, the bias current being change non-linearly with respect to the change in the reference frequency of the at least one reference clock. In another aspect, the method comprises establishing the bias current based, at least in part, on a capacitance of a reference capacitor, and changing the bias current in response to a change in the capacitance of the reference capacitor such that the bias current is changed non-linearly with respect to changes in the capacitance of the reference capacitor.

Abstract: A method of compensating a monolithic integrated operational amplifier against process and temperature variations, such that the operational amplifier is suitable for use in an active filter, the method comprising a providing an amplifier having a first stage and an output stage, wherein the output stage drives an RC load, and wherein a compensation capacitor at an output of the first stage is selected so as to scale with the capacitance C of the RC load, and a transconductance of the first stage is a function of the resistance R of the RC load.

Abstract: The intercept of a logarithmic amplifier is temperature stabilized by generating a signal having the form H log H where H is a function of temperature such as T/T0. The first H factor is cancelled, thereby generating a correction signal having the form Y log H. The cancellation may be implemented with a transconductance cell having a hyperbolic tangent function. The H log H function may be generated by a pair of junctions biased by one temperature-stable current and one temperature-dependent current. The pair of junctions and the transconductance cell may be coupled together in a translinear loop. A user-accessible terminal may allow adjustment of the correction signal for different operating frequencies.

Abstract: A voltage level shifting circuit (5) for shifting the common mode voltage of a differential signal to be within the working range of a differential input buffer circuit (3) comprises a first resistive voltage divider circuit (18) coupled between a first input terminal (10) and a voltage reference terminal (15) for receiving a voltage reference to which the common mode voltage of the level shifted differential signal is to be referenced, and a second resistive voltage divider circuit (18) coupled between a second input terminal (11) and the voltage reference terminal (15). The differential signal is applied to the first and second terminals (10,11), and the level shifted differential signal is produced on first and second output taps (17,19) of the first and second resistive voltage divider circuits (16,18) with the common mode of the level shifted differential signal referenced to the voltage reference applied to the voltage reference terminal (15).

Abstract: A DC to DC converter comprising an inductor, first and second electronically controllable switches and a controller, wherein the first electronically controlled switch is interposed between an input node and a first terminal of the inductor and the second electronically controllable switch extends between a second terminal of the inductor and the ground and where a first rectifier extends between the ground and the first terminal of the inductor and a second rectifier connects the second terminal of the inductor to an output node, wherein the controller controls the operation of the first and second switches to perform voltage step down or voltage step up, as appropriate, to achieve a desired output voltage; and wherein the controller is arranged such that the order in which the first and second switches are operated is maintained irrespective of whether the converter is stepping up the input voltage or stepping down the input voltage.

Abstract: A DAC circuit is described which includes a DAC coupled to an amplifier. The circuit is configured to dynamically change the operating range of the amplifier depending on the circuit operating requirements. In this way the DAC circuit may be operable in one of a plurality of available ranges so as to have an extended range of operation.

Abstract: An output stage, comprising a first transistor operable to pull a voltage at an output node towards a first voltage, and a rechargeable energy store having a potential difference between first and second terminals wherein the rechargeable energy store is arranged to be controllably connected between the output node and a second voltage supply such that the voltage at the output node can be driven to a voltage outside of a range defined between the first and second voltages.

Abstract: A voltage regulator system is disclosed for providing a regulated voltage supply. The voltage regulator system includes a power supply input node for receiving a power supply input voltage, a regulated voltage output node for providing a regulated output voltage, and a feedback circuit coupled to the regulated output voltage node and to a voltage regulator input node wherein a non-zero voltage is provided by the voltage regulator input node.

Abstract: A method of forming a microphone forms a backplate, and a flexible diaphragm on at least a portion of a wet etch removable sacrificial layer. The method adds a wet etch resistant material, where a portion of the wet etch resistant material is positioned between the diaphragm and the backplate to support the diaphragm. Some of the wet etch resistant material is not positioned between the diaphragm and backplate. The method then removes the sacrificial material before removing any of the wet etch resistant material added during the prior noted act of adding. The wet etch resistant material then is removed substantially in its entirety after removing at least part of the sacrificial material.

Abstract: A communication system includes a multi-channel signal regulation system that limits an aggregate signal in response to an indication that the aggregate signal exceeds a threshold value. The aggregate signal is formed from a combination of the input signals.

Abstract: An apparatus is provided for buffering instructions. An instruction store has memory locations for storing instructions. Each instruction can be associated with a timer such that an instruction dispatcher causes the instruction to be sent when the timer indicates that the instruction should be sent.

Abstract: A laser driver system is disclosed that includes a first monitor current output node, a power set node, and a first feedback path. The first monitor current output node provides a first monitor current output signal that is representative of one of a bias current and a modulation current of the laser driver system. The power set node receives a power ratio set signal that represents a desired relationship of a power required for the laser driver to produce a high power level threshold to a power required for the laser driver to produce a low power level threshold. The first feedback path extends from the first monitor current output node to the power set node, and may be used for adjusting the power set signal when the monitor current output signal becomes non-linear.

Abstract: A bandgap voltage reference circuit is described. By providing first and second bipolar devices that are operable with different current densities a base emitter voltage difference is created. This voltage difference is increased by coupling first and second cascode circuits to the first and second bipolars, the cascode circuits also being scaled relative to one another.

Abstract: A control system for a switching power supply shifts the phase of a PWM signal in response to a change in operating conditions. The phase may be shifted by resetting an oscillator that controls the PWM signal. Phase shift logic may include a sample-hold circuit that holds the value of an error signal when the PWM signal switches state. The held error signal may be compared to the real-time error signal, preferably with a user configurable offset. The output of the phase shift logic may be used to reset the oscillator.