Abstract: An electronic chip has a data input for receiving an input digital data signal with a data frequency, a plurality of switches, and a logic circuit operatively coupled with both the plurality of switches and the data input. The logic circuit controls the switches to be in one of a DAC mode or a mixer mode. The DAC mode causes the switches to convert the input digital data signal into a DAC analog signal having about the data frequency. The mixer mode, however, causes the switches to convert the input digital data signal into a mixed analog signal having a mixer frequency that is higher than the data frequency.

Abstract: A low noise voltage reference circuit is described. The reference circuit utilizes a bandgap reference component and may include at least one of a current shunt or filter to reduce high and low noise contributions to the output. Further modifications may include a curvature correction component.

Abstract: A DAC circuit is provided which implements a buffered DAC input where the buffer is provided by a differential amplifier whose supply rail is correlated with the input to the DAC. In this way it is possible to buffer the circuitry using amplifiers whose open loop gain specifications may be relaxed without affecting the linearity performance of the DAC.

Abstract: A low-noise programmable current source includes an output digital to analog converter for providing an output load current; and a control circuit, responsive to an input defining a predetermined load current for generating, for the digital to analog converter, a control word and a control voltage; the control word and the control voltage drive the digital to analog converter to produce the predetermined load current and the control voltage sets the compliance voltage of the digital to analog converter to minimize current noise in the digital to analog converter.

Abstract: A method for generating a digital signal pattern at M outputs involves retrieving an instruction from memory comprising a first set of bits identifying a first group of N outputs that includes fewer than all of the M outputs, and a second set of N bits each corresponding to a respective output included in the identified first group of N outputs. For each of the M outputs that is included in the identified first group of N outputs, the signal at the output is toggled if the one of the N bits corresponding to that output is in a first state and is kept in the same state if the one of the N bits corresponding to that output is in a second state. For each of the M outputs that is not included in the identified first group of N outputs, the signal at that output is kept in the same state.

Abstract: One disclosed circuit comprises a clock cycle counter circuit, a memory, and a clock cycle count comparison circuit. The clock cycle counter circuit may be configured to produce an output count. The memory may be configured to store at least first and second count values. The cycle count comparison circuit may be configured to compare the output count with each of the first and second stored count values and to generate a particular type of output event at a node if the output count corresponds to either of the first and second stored count values. Another disclosed circuit comprises a digital pattern generator, a general purpose output controller, at least one memory element, and a selection circuit. The digital pattern generator may be configured to generate a pattern of digital signals at M nodes. The general purpose output controller may be configured to generate general purpose digital signals at N nodes.

Abstract: An apparatus for generating a digital signal pattern may comprises a memory, a program sequencer, first and second circuits, and an event execution unit. The memory may have stored therein a plurality of instructions that, when executed, cause a digital signal pattern to be generated on a plurality of nodes. The program sequencer may be configured to control a sequence in which the plurality of instructions are retrieved from the memory and executed. The first circuit may sequentially step through a plurality of different output states in response to a clock signal. The second circuit may identify an output event when an output state of the first circuit corresponds to an output state identified by retrieved instructions of a particular type. The event execution unit may control states of signals on the plurality of nodes in a manner specified by the retrieved instructions of the particular type in response to the second circuit identifying an output event.

Abstract: Multiplication engines and multiplication methods are provided for a digital processor.

Abstract: A digital to analog converter (DAC) includes a first continuous-time stage that receives an input signal associated with a digital signal and performs continuous-time digital-to-analog conversion operations on the input signal. The first continuous-time stage outputs a first output signal. A second switched-capacitor stage receives the first output signal and performs switched-capacitor filtering of the first output signal. The second switched-capacitor stage outputs a second output signal that is sent to a low pass filter to form a continuous analog signal associated with the digital signal.

Abstract: An inertial sensor includes a cross-quad configuration of four interconnected sensor elements. Each sensor element has a frame and a resonator suspended within the frame. The sensor elements are arranged so that the frames of adjacent sensor elements are allowed to move in anti-phase to one another but are substantially prevented from moving in phase with one another. The sensor elements may be configured in a horizontally coupled arrangement, a vertically coupled arrangement, or a fully coupled arrangement. A pair of sensor elements may be vertically coupled.

Abstract: Receiver embodiments are disclosed that can process a wide range of transmission bandwidths over a wide range of transmission frequencies and provide reduced converter sampling rates, filter bandwidths, and filter tuning ranges and enhanced signal-to-noise performance. They convert transmission signals with quadrature local oscillator signals whose frequencies are commanded to be a selected transmission frequency when a selected transmission bandwidth is above a predetermined bandwidth threshold and are commanded to be offset from the selected transmission frequency by an intermediate frequency that is at least one half of the selected transmission bandwidth when the selected transmission bandwidth is below the bandwidth threshold.

Abstract: A sample and hold circuit architecture samples using two capacitors that are cyclically switched between charge and discharge modes. The sample and hold circuit includes a buffer to receive an input signal to be sampled, a first sampling capacitor, a second sampling capacitor, and an amplifier. The first sampling capacitor is connected to the output of the buffer during the positive phase of a clock and across the feedback path of the amplifier during the zero phase of the clock. The second sampling capacitor is connected to the output of the buffer during the zero phase of the clock and across the feedback path of the amplifier during the positive phase of the clock. Neither the first sampling capacitor nor the second sampling capacitor is simultaneously connected to the buffer, the amplifier, or to each other.

Abstract: A method and an apparatus provide extraction of data from an analog signal. The method includes deriving a data-location signal having amplitude transitions that identify a phase of amplitude transitions of the analog signal, and, in response to the data-location signal, selecting a sampling clock signal having a phase different from the phase of the amplitude transitions of the analog signal. The apparatus includes a signal generator that derives from the analog signal a data-location signal, and a selector that selects a sampling clock signal having a phase different from the phase of the amplitude transitions of the analog signal.

Abstract: A mismatch shaping ?? analog to digital converter system includes a plurality of internal ?? analog to digital submodulators to provide an output; a feedback circuit including a feedback digital to analog converter responsive to the output; a summing circuit for providing the difference of an analog input and the output of the feedback circuit; and a loop filter responsive to the summing circuit and having a plurality of stages, the last stage of which is distributed to and functions as a loop filter stage in each of the plurality of analog to digital submodulators for attenuating the mismatch noise of the feedback digital to analog converter in the pass band of the ?? analog to digital converter system.

Abstract: An advanced encryption standard (AES) engine with real time S-box generation includes a Galois field multiplier system in a first mode responsive to a first data block for generating an AES selection (S-box) function by executing the multiplicative increase in GF1(2m) and applying an affine over GF(2) transformation to obtain a subbyte transformation; and a shift register system for transforming the subbyte transformation to obtain a shift row transformation; the Galois field multiplier system is responsive in a second mode to the shift row transformation to obtain a mix column transformation and add a round key for generating in real time an advanced encryption standard cipher function of the first data block.

Abstract: A method for one-way coupling an input signal to an integrated circuit on a semiconductor chip with the integrated circuit electrically isolated from the input signal comprises forming a MOS isolation coupler on the semiconductor chip by a CMOS process. The MOS isolation coupler comprises an inductor coil for generating a magnetic field in response to an input signal applied to terminals thereof. A MAGFET having a split drain formed by respective drain portions is formed on the semiconductor chip below the inductor coil, so that a current difference is induced between the drain currents in the drain portions which is proportional to the strength of the magnetic field generated by the inductor coil resulting from the input signal. The MAGFET is formed prior to the inductor coil. An oxide isolating layer is provided over the MAGFET, and the inductor coil is formed on the oxide layer.

Abstract: A phase lock loop RF modulator system including a phase lock loop circuit having a phase detector circuit responsive to an input reference signal and a feedback signal, an oscillator circuit responsive to the phase detector circuit for providing an output signal, a forward path from the phase detector circuit to the oscillator circuit, and a feedback path from the oscillator circuit to the phase detector circuit. The system also includes a first modulation port coupled to the feedback path, a second modulation port coupled to the forward path, and a gain mismatch detection circuit responsive to modulation data and a phase error between the reference signal and the feedback signal for providing an indicator output signal that represents the gain mismatch between the first modulation port and the second modulation port.

Abstract: A package apparatus has a base coupled with a lid to form a leadframe package. The package has first and second exterior surfaces with respective first and second contact patterns. The first and second contact patterns are substantially electrically identical to permit the package to be either vertically or horizontally mounted to an underlying apparatus.

Abstract: The invention provides a sensor including a first sensor element formed in a first substrate and at least one optical element formed in a second substrate, the first and second substrates being configured relative to one another such that the second substrate forms a cap over the first sensor element. The cap includes a diffractive optical element and an aperture stop which collectively determine the wavelength of incident radiation that is allowed through the cap and onto the at least one optical element.

Abstract: A method of producing a MEMS device removes the bottom side of a device wafer after its movable structure is formed. To that end, the method provides the device wafer, which has an initial bottom side. Next, the method forms the movable structure on the device wafer, and then removes substantially the entire initial bottom side of the device wafer. Removal of the entire initial bottom side effectively forms a final bottom side.