Patents Assigned to Analog Devices, Inc.
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Patent number: 6433632Abstract: A switched capacitor correlated double sampling circuit includes an op amp, an input sampling capacitor, and a feedback capacitor. The input capacitor samples the input signal during a first time phase and the feedback capacitor receives the signal charge from the input capacitor. No sampling switch is located between the input capacitor and the input terminal.Type: GrantFiled: May 26, 2000Date of Patent: August 13, 2002Assignee: Analog Devices, Inc.Inventors: Katsufumi Nakamura, Steven Decker
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Patent number: 6429697Abstract: A multi-stage, low-offset, fast-recovery, comparator system and method for: reducing the input offset voltage of the zeroing amplifier by a factor essentially equal to gain of the zeroing amplifier; reducing the input offset voltage of the combined main and zeroing amplifiers by a factor essentially equal to the product of the gains of the main and zeroing amplifiers; and amplifying the input signal to the amplification stage in accordance with the gain of the main amplifier to generate an amplified high-resolution signal.Type: GrantFiled: October 5, 1999Date of Patent: August 6, 2002Assignee: Analog Devices, Inc.Inventors: Bruce Edward Amazeen, Michael C. W. Coln, Scott Wayne, Gerald A. Miller, Mick Mueck
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Patent number: 6429720Abstract: An RMS-DC converter provides extended dynamic range by driving a squaring cell with a variable gain amplifier. Temperature effects in the squaring cell can be cancelled by driving a second squaring cell with a reference signal and averaging the difference between the output signals from the two squaring cells. In a transmission system utilizing a power measurement system having two detector cells, square-law conformance errors in the detector cells can be cancelled by driving one of the detectors cells with a replica of the baseband modulation signal.Type: GrantFiled: May 12, 2000Date of Patent: August 6, 2002Assignee: Analog Devices, Inc.Inventor: Barrie Gilbert
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Patent number: 6429637Abstract: An electronic power meter for metering the consumption of electrical energy on power lines includes phase compensation on current transformers, whereby the acquisition of one of the two samples for the current signals is delayed and time shifted averaged, such that the average of the two signals provides a compensated signal. The amount of delay is determined from the phase lag the current transformers exhibit during the process of calibration for phase compensation. The amount of compensation that is applied varies with current, thus compensation for the non-linearity in the phase shift for the current transformers. The degree of non-linearity is computed which results in only two variables that define the phase lag at higher current and the degree of non-linearity. The technique helps in using inexpensive current transformers in the meter.Type: GrantFiled: August 4, 2000Date of Patent: August 6, 2002Assignee: Analog Devices, Inc.Inventor: Guljeet S. Gandhi
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Patent number: 6429712Abstract: A precision SET-RESET logic circuit and operating method separate a latch function from the critical signal path which produces the logic outputs. In a particular implementation the logic circuit includes two differential switch pairs controlled respectively by SET and RESET inputs, with respective enable circuits for the differential pair controlled by the output of the latch circuit. The SET and RESET differential switch pairs respond faster than the latch circuit to a change to the input SET-RESET state. A logic output is initially produced by establishing a first current path through. the differential switches and enable circuits in response to a new logic input, and then latched via a different current path.Type: GrantFiled: August 29, 2001Date of Patent: August 6, 2002Assignee: Analog Devices, Inc.Inventors: Thomas A. Gaiser, Kenneth J. Stern, Farhad Vazehgoo, Vincenzo DiTommaso, William L. Walter, Edward B. Hilton
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Publication number: 20020103991Abstract: In one embodiment, a pipelined processor is described that includes an execution pipeline having a plurality of stages and a multi-cycle instruction (MCI) controller adapted to assert a stall signal to stall the multi-cycle instruction within one of the stages of the execution pipeline. The MCI controller is adapted to issue a plurality of instructions to subsequent stages in the pipeline while the multi-cycle instruction is stalled.Type: ApplicationFiled: December 6, 2000Publication date: August 1, 2002Applicant: Intel Corporation and Analog Devices, Inc.Inventors: Gregory A. Overkamp, Charles P. Roth, Ravi P. Singh
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Patent number: 6426712Abstract: Resolver systems are described that generate an estimate &phgr; of a rotatable member's position angle &thgr; and provide fault signals which monitor the reliability and accuracy of the estimate. The fault signals are formed from a monitor signal which multiplies resolver and estimate signals to derive information on the absolute and relative levels of resolver sense signals. At least one fault signal is formed from a loop error signal of the system servo loop. The fault signals report on, for example, mismatched sense signals, out-of-range sense signals and loss of position tracking to thereby enhance accuracy and safety in various resolver applications.Type: GrantFiled: November 16, 2000Date of Patent: July 30, 2002Assignee: Analog Devices, Inc.Inventors: Bruce Hare, Aengus Murray
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Patent number: 6426268Abstract: A thin film resistor fabrication method requires that an IC's active devices be fabricated on a substrate, and a dielectric layer be deposited over the devices to protect them from subsequent process steps. A layer of thin film material is deposited next, followed by a barrier layer and a first layer of metal. These three layers are patterned and etched to form isolated material stacks wherever a TFR is to be located, and a first level of metal interconnections. The first metal layer is removed from the TFR stacks, and the barrier layer is patterned and etched to provide respective openings which define the active areas of each TFR. In a preferred embodiment, a dielectric layer is deposited after the first metal layer is removed, to protect the interconnect metal from corrosion and as an adhesion layer for the patterning of the openings which define resistor length.Type: GrantFiled: September 7, 2001Date of Patent: July 30, 2002Assignee: Analog Devices, Inc.Inventors: Gilbert L. Huppert, Michael D. Delaus
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Patent number: 6414616Abstract: An improved voltage scaling DAC responsive to an N-bit input code word having M LSBs including first and second outer impedance string segments, each comprising 2N−M−1 series-connected impedances of substantially equal value, an inner string of series-connected impedances of substantially equal value having first and second end points, first and second outer string switch networks providing electrical connections between selected outer string impedance terminals and first and second common nodes, and an inner string switch network providing electrical connection between selected inner string impedance terminals and an output node. The inner string of series-connected impedances comprises no more than 2M−1 impedances of substantially equal value. A method for adjusting the gain of a voltage scaling DAC is also described.Type: GrantFiled: June 22, 2000Date of Patent: July 2, 2002Assignee: Analog Devices, Inc.Inventor: Dennis A. Dempsey
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Patent number: 6414974Abstract: A control circuit (10) controls the operation of a laser diode (1) for controlling the average power output (Pav) and the extinction ratio. A state machine (21) controls the control circuit (10) which reads the current from a monitor photo diode (2) which is coupled to the laser diode (1). An amplifier (20) determines the average power output of the laser diode (1) which is fed to a first comparator (23). The first comparator (23) compares the average power output with a reference value set by a resistor (R3). The output from the comparator (23) is fed to the up/down pin of a first counter (25) which is clocked by the state machine (21). In the event that the average power output is too high the first counter (25) decreases the bias current to the laser diode (1) outputted by a constant current source (5), and vice versa.Type: GrantFiled: September 7, 1999Date of Patent: July 2, 2002Assignee: Analog Devices, Inc.Inventors: Brian Keith Russell, Peter Real
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Patent number: 6414496Abstract: Comparator methods and structures are provided whose accuracy in analyzing an output signal Sout of a DUT is enhanced because they compensate for a signal distortion that is imposed by a transmission path over which the output signal Sout is received. The methods include the steps of a) providing a reference signal Sref; b) combining the reference signal Sref with a reference distortion that corresponds to the signal distortion to thereby realize a compensated reference signal Scmp-ref; and c) comparing the output signal Sout to the compensated reference signal Scmp-ref to determine signal parameters of the output signal Sout. The methods of the invention facilitate the use of simple comparator structures that do not significantly increase the cost of automatic test equipment but which do significantly increase accuracy of signal analysis.Type: GrantFiled: June 16, 2000Date of Patent: July 2, 2002Assignee: Analog Devices, Inc.Inventor: Christopher McQuilkin
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Patent number: 6411330Abstract: A detector circuit (1) for detecting the presence or absence of a television (2) on an output (3) of a video DAC (4) comprises a comparator (11) for comparing a voltage developed by the video signal on a control resistor R2 with a reference voltage of 0.5 volts. The resistor R2 is of 75 ohms and matches the internal impedance R1 of 75 ohms of the television (2). A latch (12) latches the output from the comparator (11) onto an output pin Q when the voltage developed across the control resistor R2 is developed by an equalisation pulse of the vertical blanking interval of the video signal. In the presence of a television (2) the voltage developed across the control resistor R2 is 0.35 volts, which pulls the output of the comparator (11) low, while in the absence of a television (2) the voltage developed across the control resistor R2 is 0.7 volts which pulls the output of the comparator (11) high.Type: GrantFiled: June 10, 1998Date of Patent: June 25, 2002Assignee: Analog Devices, Inc.Inventors: John Patrick Purcell, Vincent James Troy, Kieran Heffernan
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Publication number: 20020078336Abstract: In one embodiment, a method is disclosed for holding instruction fetch requests of a processor in an extended reset. Fetch requests are disabled when the processor undergoes a reset. When the reset is completed, fetch requests remain disabled when the instruction memory is being loaded. When loading of the instruction memory is completed, fetch requests are enabled.Type: ApplicationFiled: December 15, 2000Publication date: June 20, 2002Applicant: Intel Corporation and Analog Devices, Inc.Inventors: Ravi P. Singh, Charles P. Roth, Ravi Kolagotla, Juan G. Revilla
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Publication number: 20020078333Abstract: In one embodiment, a programmable processor is adapted to support hardware loops. The processor may include hardware such as a first set of registers, a second set of registers, a first pipeline, and a second pipeline. Furthermore, the processor may include a control unit adapted to efficiently implement the hardware when performing a hardware loop.Type: ApplicationFiled: December 20, 2000Publication date: June 20, 2002Applicant: Intel Corporation and Analog Devices, Inc.Inventors: Ryo Inoue, Ravi P. Singh, Charles P. Roth, Gregory A. Overkamp
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Publication number: 20020078326Abstract: In one embodiment, a programmable processor is adapted to include a speculative count register. The speculative count register may be loaded with data associated with an instruction before the instruction commits. However, if the instruction is terminated before it commits, the speculative count register may be adjusted. A set of counters may monitor the difference between the speculative count register and its architectural counterpart.Type: ApplicationFiled: December 20, 2000Publication date: June 20, 2002Applicant: Intel Corporation and Analog Devices, Inc.Inventors: Charles P. Roth, Ravi P. Singh, Gregory A. Overkamp
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Publication number: 20020078334Abstract: In one embodiment, a programmable processor includes a execution pipeline and an exception pipeline. The execution pipeline may be a multi-stage execution pipeline that processes instructions. The exception pipeline may be a multi-stage exception pipeline that propagates exceptions resulting from the execution of the instructions. The first and exception pipelines may have the same number of stages and may operate on the same clock cycles. When an instruction passes from a stage of the execution pipeline to a later stage of the execution pipeline, an exception may similarly pass from a corresponding stage of the exception pipeline to a corresponding later stage of the exception pipeline.Type: ApplicationFiled: December 15, 2000Publication date: June 20, 2002Applicant: Intel Corporation and Analog Devices, Inc.Inventors: Charles P. Roth, Ravi P. Singh, Gregory A. Overkamp
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Patent number: 6404825Abstract: A digital radio tuner lock detector receives an in-phase (I) data signal and a quadrature (Q) data signal. The lock detector processes these signals to compute a data signal power estimate and integrates the data signal power estimate to provide a threshold signal value. The lock detector also includes a carrier frequency lock detector and a carrier phase lock detector. The carrier frequency lock detector receives the I and Q data signals and computes a frequency error signal and integrates the frequency error signal to provide an integrated frequency error signal. The carrier frequency lock detector compares the magnitude of the integrated frequency error signal to the threshold signal value to determine if frequency lock has been achieved and provides a frequency lock status signal indicative thereof. The carrier phase lock detector receives the I and Q data signals and computes a phase error signal and integrates the phase error signal to provide an integrated phase error signal.Type: GrantFiled: March 24, 1999Date of Patent: June 11, 2002Assignee: Analog Devices, Inc.Inventor: Dimitrios Efstathiou
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Patent number: 6400541Abstract: A circuit protects differential inputs of circuitry, such as RF circuitry, against electrostatic discharge. The circuit includes first and second diodes connected in opposite directions between a first differential input pin and a virtual ground node, third and fourth diodes connected in opposite directions between a second differential input pin and the virtual ground node, a first protection device connected between the virtual ground node and a first external pin, such as a positive supply pin, and a second protection device connected between the virtual ground node and a second external pin, such as a negative supply pin. The first and second protection devices may be fifth and sixth diodes, respectively. Because no signal appears at the virtual ground node, the fifth and sixth diodes can be relatively large.Type: GrantFiled: April 3, 2000Date of Patent: June 4, 2002Assignee: Analog Devices, Inc.Inventor: Stephen Jonathan Brett
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Patent number: 6400227Abstract: A variable gain amplifier has at least two branches connected in parallel to drive a common output load. Each branch includes at least two FETs in a cascode configuration. A first FET in each branch is arranged to receive an input signal and to amplify the signal in a common source configuration; the second FET is arranged in a common gate configuration with its source receiving the output current of the first FET. The gate of the second FET is coupled to a corresponding gain control input so that the second FET is enabled when the gate receives an enabling gain control signal and disabled otherwise. Preferably the first and second FETs in each branch are biased in a saturation region of operation when the second FET is enabled by the gain control input. This maintains a low distortion figure throughout the dynamic range of the gain control. Preferably, the invention also includes an active fixed gain power amplification stage for coupling the output to a power amplifier.Type: GrantFiled: May 31, 2001Date of Patent: June 4, 2002Assignee: Analog Devices, Inc.Inventors: Marc Goldfarb, Rosamaria Croughwell, Peter Katzin
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Patent number: 6400302Abstract: Quasi-differential successive-approximation methods and structures are provided for converting analog signals into corresponding digital signals. These methods and structures realize the signal-to-noise improvements of fully-differential SAR ADCs and the calibration accuracy improvements of pseudo-differential SAR ADCs. Structures of the invention operate in a fully-differential mode to establish more-significant bits of the corresponding digital signals and in a pseudo-differential mode to establish the less-significant bits.Type: GrantFiled: February 26, 2001Date of Patent: June 4, 2002Assignee: Analog Devices, Inc.Inventors: Bruce Edward Amazeen, Michael Christian Wohnsen Coln, Gary Robert Carreau