Abstract: In one embodiment, a processor receives coded instructions and converts the instructions to a second code prior to execution. The processor may be a digital signal processor. A decoder in the processor determines the destination of the instructions and performs decoding functions based on the destination.

Abstract: Methods and apparatus for calibrating one or more signals of an electronic device are provided. Calibration coefficients are stored in a memory, such as a fuse bank, to be applied to correct the one or more signals. A selection multiplexer is provided, the selection multiplexer capable of assigning one of a number of bit weight configurations to the calibration coefficients to set a desired range and resolution for calibration information applied to the one or more signals of the electronic device.

Abstract: Comparator systems are provided that include first and second differential pairs of transistors with inherent offsets that are a function of their tail currents. Some system embodiments configure the pairs to have substantially-equal, nonzero inherent offset voltages and other embodiments configure them to have substantially-zero inherent offset voltages. The systems further include a feedback network arranged to provide a second tail current to the second differential pair that substantially nulls the second output signal of this differential pair when it is driven by a reference signal. The feedback network generates an identical first tail current for the first differential pair which will now accurately compare an input signal to the reference signal.

Abstract: A variable capacitance switched capacitor input system and method includes a differential integrator circuit having first and second input summing nodes and a variable sensing capacitor; one terminal of the variable sensing capacitor is connected to one of the nodes in the first phase and to the other of the nodes in the second phase; an input terminal connected to a second terminal of the variable sensing capacitor receives a first voltage level in the first phase and a second voltage level in the second phase for delivering the charge on the variable sensing capacitor to the first summing node in the first phase and to the second summing node in the second phase and canceling errors in a differential integrator circuit output caused by leakage current.

Abstract: A coupler circuit for sampling an output power of a signal from an output power source has at least one first sampling element for sampling a first portion of the signal and at least one second sampling element for sampling a second portion of the signal. The first sampling element and the second sampling element are separated by an output matching network defined by a set of S-parameters. A processor coupled to the at least one first and second sampling elements determines the output power based on at least the first portion of the signal and the second portion of the signal. A detector may be coupled to the processor to measure whether the first and second portion of the signal or the output power determined by the processor.

Abstract: A drive circuit for a brushless DC motor includes a switch constructed and arranged to drive the motor with a pulse signal responsive to a control signal, and control circuitry coupled to the switch and constructed and arranged to generate the control signal responsive to rotor position information from the motor so as to synchronize the pulse signal to the rotor position. A current sensing device can be used to provide the rotor position information to the control circuitry by sensing current flowing through the motor.

Abstract: Methods and apparatus for amplifying a tuner input signal are disclosed. One embodiment of the invention is directed to a tuner amplifier system comprising a tuner amplifier input that receives a tuner amplifier input signal and a first amplifier comprising an input and an output. The input of the first amplifier is coupled to the tuner amplifier input. The system further comprises a second amplifier comprising an input and an output, the input of the second amplifier being coupled to the tuner amplifier input, and a switch adapted to couple one of the first amplifier output and the second amplifier output to an output of the tuner amplifier. Another embodiment of the invention is directed to a method of amplifying a tuner input signal. The method comprises acts of detecting a power of the tuner input signal, selecting a tuner amplifier to amplify the tuner input signal based on the power of the tuner input signal, and amplifying the tuner input signal using the selected amplifier.

Abstract: Methods and apparatus for tuning are disclosed. One embodiment of the invention is directed to a tuner formed on a substrate. The tuner comprises a first die that receives an analog input signal and processes the analog input signal using analog processing circuitry to form analog output signals, and a second die that receives the analog output signals, converts the analog output signals to digital signals, and processes the digital signals to form output signals. Another embodiment of the invention is directed to a multi-chip module comprising a tuner adapted to process television signals of a plurality of types and of a plurality of standards to form output signals.

Abstract: A wideband impedance attenuator includes a phase-locked loop filter, a voltage-controlled oscillator connected to the phase-locked loop filter during transmit, and an impedance circuit connected to the phase-locked loop filter and the voltage controlled oscillator. The impedance circuit is a scaled version of the phase-locked loop filter. Moreover, the wideband impedance attenuator attenuates a Gaussian frequency shift key modulation signal by a factor of 1/(N+1) using the impedance circuit, which has an impedance of N*Z(s), and the phase-locked loop filter, which has an impedance of Z(s). An output frequency is generated using a voltage-controlled oscillator wherein the output frequency corresponds to the attenuated Gaussian frequency shift key modulation signal. In addition, a comparator compares a voltage of an output from the programmable gain amplifier with a voltage necessary to produce a predetermined frequency shift in a voltage-controlled oscillator to produce a gain signal.

Abstract: A bipolar differential input stage with an input bias current cancellation circuit comprises an input pair and a bipolar tracking transistor. The input stage is arranged such that the collector currents in the input pair and tracking transistor, and the collector-emitter voltages of the input pair and tracking transistor, are substantially equal. A lateral PNP transistor's first collector provides the tracking transistor base current required to achieve the substantially equal collector current, and second and third collectors provide copies of the tracking transistor base current as bias current cancellation currents to the bases of the input pair, thereby reducing the input stages' input bias currents.

Abstract: One embodiment of the invention is directed to a method comprising an act of performing digital correction of an offset in a system comprising an analog-to-digital converter (ADC) having a usable input range that is greater than a nominal input range, wherein the offset exists at an input of the ADC. Another embodiment of the invention is directed to a system comprising an ADC having a usable input range that is greater than a nominal input range, wherein an offset exists at an input of the ADC and the offset is corrected using digital correction.

Abstract: A method of forming a MEMS device produces a device layer wafer having a pre-formed conductive pathway before coupling it with a handle wafer. To that end, the method produces the noted device layer wafer by 1) providing a material layer, 2) coupling a conductor to the material layer, and 3) forming at least two conductive paths through at least a portion of the material layer to the conductor. The method then provides the noted handle wafer, and couples the device layer wafer to the handle wafer. The wafers are coupled so that the conductor is contained between the material layer and the handle wafer.

Abstract: A flip-bonding technique is used to fabricate complex micro-electromechanical systems. Various micromachined structures are fabricated on the front side of each of two wafers. One of the wafers is flipped over and bonded to the other wafer so that the front sides of the two wafers are bonded together in a flip-stacked configuration.

Abstract: A translinear amplifier is disclosed. A loop amplifier drives the bases of the input and output transistor pairs from the differential collector voltage of the input pair. The loop amplifier contains a third differential pair (a gain pair). The tail current of the gain pair is inversely related to the tail current of the input pair, such that loop amplifier gain remains stable when the transconductance of the input pair changes (due, e.g., to input gain changes). In one embodiment, a linear-in-dB interface is provided that adjusts input pair tail current exponentially (and gain pair tail current exponentially and inversely) to linear voltage changes at a gain input.

Abstract: A memory system for operation with a processor, such as a digital signal processor, includes a high speed pipelined memory, a store buffer for holding store access requests from the processor, a load buffer for holding load access requests from the processor, and a memory control unit for processing access requests from the processor, from the store buffer and from the load buffer. The memory control unit may include prioritization logic for selecting access requests in accordance with a priority scheme and bank conflict logic for detecting and handling conflicts between access requests. The pipelined memory may be configured to output two load results per clock cycle at very high speed.

Abstract: A common mode linearized input stage comprises NPN and PNP differential pairs biased with respective tail currents at respective common emitter nodes, with each pair connected to receive a differential input signal. A tail current modulation circuit generates complementary output currents as a function of the voltage difference between the common emitter nodes, and first and second tail current sources generate the tail currents as a function of the complementary output currents. The tail current modulation circuit and the first and second tail current sources are arranged such that the magnitudes of the tail currents increase with an increasing differential input signal.

Abstract: An improved pipelined analog to digital converter that facilitates calibration for non-linearity errors and a method for obtaining calibration values. The analog to digital converter has a calibration mode in which the output bits for stages in the pipeline can be coupled to output pins of the device. Device pins that are used in normal operating mode to output the most significant bits of the ADC output are used in calibration mode to make available output bits of a pipeline stage being calibrated. A calibration method takes advantage of the outputs of the stages being directly observable to compute calibration values. The output bits of a pipeline stage are monitored as the analog input to the ADC is increased. A change in these bits identifies a subrange boundary. Errors are measured for values immediately above and immediately below each subrange boundary and used to compute correction factors.

Abstract: The invention provides a new approach which is better suited to FFT design as applied to multicarrier modulation systems such as OFDM. The signals are scaled so that overflow, rather than being completely avoided, occurs with low probability throughout the IFFT and FFT structures. The size of the error that results from an overflow depends on how overflow is handled in the DSP. To minimize the degradation, overflow should result in saturation of the value at the maximum positive or negative value option. This is equivalent to clipping the signal. Using the new technique, signals within the FFT structure are scaled to balance the effect of clipping and round-off. Clipping may result in comparatively large errors in a few signal values but because of the spreading effect of the FFT and because OFDM systems typically include error coding/correction, system performance depends on the total error or, in other words the total noise power, across all of the FFT outputs rather than on any individual value.

Abstract: A digital blanking circuit allows a first digital input signal transition to be passed on to a following stage, but prohibits the passing of subsequent transitions for a predetermined blanking interval. One embodiment of the present invention employs rising edge and falling edge latches, the inputs of which receive the digital input signal and the outputs of which are connected to a two-to-one multiplexer. The mux output is connected to a blanking interval circuit, which is triggered to begin timing a blanking interval by a multiplexer output transition. The blanking interval circuit provides outputs which control the latches and selects the latch output to be transferred to the multiplexer output such that the multiplexer output is prevented from transitioning during a blanking interval.

Abstract: A current integration circuit includes an operational amplifier having a capacitor connected between its output and inverting input which integrates an input current. To prevent the op amp's output from becoming saturated, a charge dumping circuit dumps a known charge of the opposite polarity to that stored on the capacitor to the op amp's inverting input, thus reducing the charge on the capacitor and preventing the op amp's output from becoming saturated. A charge dump is triggered whenever the op amp's output exceeds a predetermined trip voltage. Counting the number of charge dumps performed during a given integration period provides a coarse indication of the magnitude of the integrated input current, and the output of the op amp provides a fine indication.