Abstract: Methods and apparatus for reducing the thermal noise integrated on a storage element are disclosed. One embodiment of the invention is directed to a sampling circuit comprising a sampling capacitor to store a charge, the sampling capacitor being exposed to an ambient temperature. The sampling circuit further comprises circuitry to sample the charge onto the capacitor, wherein thermal noise is also sampled onto the capacitor, and wherein the circuitry is constructed such that the power of the thermal noise sampled onto the capacitor is less than the product of the ambient temperature and Boltzmann's constant divided by a capacitance of the sampling capacitor. Another embodiment of the invention is directed to a method of controlling thermal noise sampled onto a capacitor. The method comprises an act of independently controlling the spectral density of the thermal noise and/or the bandwidth of the thermal noise.

Abstract: A universally accessible fully programmable memory built-in self-test (MBIST) system including an MBIST controller having an address generator configured to generate addresses for a memory under test, a sequencer circuit configured to deliver test data to selected addresses of the memory under test and reading out that test data, a comparator circuit configured to compare the test data read out of the memory under test to the test data delivered to the memory under test to identify a memory failure, and an externally accessible user programmable pattern register for providing a pattern of test data to the memory under test. The system includes an external pattern programming device configured to supply the pattern of test data to the user programmable data pattern register.

Abstract: Computer-implemented techniques are provided for synthesizing sounds of an internal combustion engine vehicle using a physical model of the vehicle. In general terms, the method includes independently generating and/or synthesizing separate components of the vehicle sound, then combining these components to produce a final sound. Using a physical model of the vehicle, the separate components of the vehicle sound are independently generated from vehicle control parameters characterizing the operating conditions of the vehicle. The components are then combined using mixers and equalizers to produce a realistic vehicle sound. The present technique allows independent control of the separate components of the vehicle sound, is not limited to specific vehicles, and does not require recorded sounds taking large amounts of storage space.

Abstract: Input and output sections of an analog-to-digital converter are joined by an interface. In the input section, an analog input signal is converted to a multi-bit digital signal before being converted, by a noise-shaping converter such as a sigma-delta modulator, to a lower bit signal. The lower bit signal is carried across the interface before being converted, by a digital filter to recover the original multi-bit signal. The same principle is applied to the input and output sections of a digital-to-analog converter.

Abstract: A switched noise filter circuit for DC-DC converters which use the instantaneous output voltage to establish the converter's duty ratio. The converter cycles the switching element on and off for time intervals Ton and Toff, respectively. A switching control circuit includes a filter capacitance connected between the feedback node and ground, and a comparator which compares a feedback voltage Vfb with a fixed voltage Vref; at least one of Ton and Toff is a “modulated” interval which is terminated when Vfb crosses Vref due to the discharge of the filter capacitance. A switched noise filter circuit applies an offset voltage to Vfb during at least one of Ton, and Toff, with the offset voltage disconnected from Vfb by the beginning of the modulated interval or shortly thereafter. When the offset voltage is properly applied, the effect of extraneous electromagnetic noise coupled into Vfb is reduced.

Abstract: A memory is provided in which each memory cell can be in a first state or a second state, and those cells which should be in the first state always correctly power up into that state whereas cells which should be in the second state may power up incorrectly. A counting arrangement is provided to count the number of cells in either of the states and to compare this with a predetermined number. If the numbers do not match, a memory reset is performed. The memory cells can be constructed from a single fusible element thereby saving space whilst also consuming substantially zero power following power up.

Abstract: A high side current monitor circuit includes an op amp which is coupled across a sensing element which carries a current Isense and develops a shunt voltage Vsense. A feedback transistor driven by the op amp output conducts an output current Iout through a resistor to a current output node necessary to make the op amp inputs equal, such that Iout is proportional to Isense. Iout is conducted through a resistor to generate a ground-referred voltage proportional to Vsense. When the common mode voltage of Vsense is greater than the op amp's breakdown voltage, a discrete transistor is connected between the current output node and ground to stand off the voltage across the amp. The monitor circuit is arranged such that it can be powered with a limited fraction of the common mode voltage when used with a discrete transistor, and is self-biased when used without a discrete transistor.

Abstract: A metallization stack is provided for use as a contact structure in an integrated MEMS device. The metallization stack comprises a titanium-tungsten adhesion and barrier layer formed with a platinum layer formed on top. The platinum feature is formed by sputter etching the platinum in argon, followed by a wet etch in aqua regia using an oxide hardmask. Alternatively, the titanium-tungsten and platinum layers are deposited sequentially and patterned by a single plasma etch process with a photoresist mask.

Abstract: A semiconductor substrate (1) comprising an SOI (2) formed therein. The semiconductor substrate (1) comprises first and second wafers (4,6) which are directly bonded together along a bond interface (9). Prior to bonding the wafers (4,6), a portion (15) of the second wafer (6) is ion implanted to form a p+ region for facilitating selective etching thereof to form a buried cavity (16), in which a buried insulating layer is subsequently formed under a portion (10) of the first wafer (4) for forming the SOI (2). After bonding of the first and second wafers (4,6) a communicating opening (20) is etched through the first wafer (4) to the bond interface (9), and the selectively etchable portion (15) is etched through the communicating opening (20) to form the buried cavity (16). The buried cavity (16) is then filled with deposited oxide to form the buried insulating layer (11).

Abstract: An electronic device, such as a microprocessor, with a timing circuit. The timing circuit contains a phase locked loop that, during a first interval, checks whether a control signal in the phase locked loop is between a maximum allowed value and a minimum allowed value. When the control signal in the phase locked loop is above a maximum allowed value or below a minimum allowed value, the control circuit disables the phase locked loop for a second interval. When the control signal in the phase locked loop is below a maximum allowed value and above a minimum allowed value, the timing circuit indicates that the output of the phase locked loop is stable.

Abstract: Methods and apparatus are provided for clock domain conversion in digital processing systems. The methods include operating a first circuit in a fast clock domain with a fast clock and operating a second circuit in a slow clock domain with a slow clock. To transfer signals from the fast clock domain to the slow clock domain, a first synchronization signal is asserted during each fast clock cycle in which a slow clock edge occurs. A fast signal is transferred from the fast clock domain to the slow clock domain on a fast clock edge when the first synchronization signal is asserted. To transfer signals from the slow clock domain to the fast clock domain, a second synchronization signal is asserted during each fast clock cycle that immediately follows a slow clock edge. A slow signal is transferred from the slow clock domain to the fast clock domain on a fast clock edge when the second synchronization signal is asserted.

Abstract: A clock enable system for a multichip device includes a first integrated circuit including a clock signal and at least a second integrated circuit including at least one functional block periodically requiring clock signals from the first integrated circuit; a clock required circuit responsive to each functional block for providing a clock required signal in response to activation of any one or more of the functional blocks; and a clock enable circuit responsive to the clock required signal for enabling the first integrated circuit to provide clock signals to the functional blocks on the second integrated circuit.

Abstract: A method and a processor for processing two digital video signals clocked by respective clock signals of identical frequency but with a constant phase shift therebetween. Standard definition and progressive scan digital video signals which are clocked at first and second clock signals CLOCK—1 and CLOCK—2, respectively, of identical frequency with a constant phase shift therebetween are interfaced with a processing circuit (7) by an interface circuit (10). The progressive scan signal is clocked into a first register (20) on the second clock signal CLOCK—2, and is clocked to a second register (21) by the first clock signal CLOCK—1 and in turn to a third register (22) by the first clock signal CLOCK—1. The edge of the first clock signal CLOCK—1 on which the progressive scan signal is clocked into the second register (21) is chosen to allow sufficient time to clock the signal.

Abstract: The present invention is directed to an echo canceller adapted for use in a communication system that includes a hybrid circuit. The echo canceller comprises an adaptive digital filter that generates an estimated echo signal {circumflex over (z)}[k] in response to: (i) a sampled input data sequence x[k] and (ii) an error signal sequence e[k] indicative of the difference between a near end signal sequence y[k] and the estimated echo signal {circumflex over (z)}[k]. The adaptive digital filter computes filter coefficients based upon the error signal sequence e[k] using a stochastic quadratic descent estimator, such as for example a least mean square (LMS) estimator, that employs a dynamically adjustable step size vector ?[k].

Abstract: In one embodiment, a programmable processor searches an array of N data elements in response to N/M machine instructions, where the processor has a pipeline configured to process M data elements in parallel. In response to the machine instructions, a control unit directs the pipeline to retrieve M data elements from the array of elements in a single fetch cycle, concurrently compare the data elements to M current extreme values, and update the current extreme values, as well as M references to the current extreme values, based on the comparisons.

Abstract: A wafer cap protects micro electromechanical system (“MEMS”) structures during a dicing of a MEMS wafer to produce individual MEMS dies. A MEMS wafer is prepared having a plurality of MEMS structure sites thereon. Upon the MEMS wafer, the wafer cap is mounted to produce a laminated MEMS wafer. The wafer cap is recessed in areas corresponding to locations of the MEMS structure sites on the MEMS wafer. The capped MEMS wafer can be diced into a plurality of MEMS dies without causing damage to or contaminating the MEMS die.

Abstract: A wafer cap protects micro electromechanical system (“MEMS”) structures during a dicing of a MEMS wafer to produce individual MEMS dies. A MEMS wafer is prepared having a plurality of MEMS structure sites thereon. Upon the MEMS wafer, the wafer cap is mounted to produce a laminated MEMS wafer. The wafer cap is recessed in areas corresponding to locations of the MEMS structure sites on the MEMS wafer. The capped MEMS wafer can be diced into a plurality of MEMS dies without causing damage to or contaminating the MEMS die.

Abstract: A packaged microchip has a stress sensitive microchip, a package having a package modulus of elasticity, and an isolator between the microchip and the package. The isolator has an isolator modulus of elasticity that has a relationship with the package modulus of elasticity. This relationship causes no more than a negligible thermal stress to be transmitted to the microchip.

Abstract: A bond pad structure for an integrated circuit includes first and second active devices formed in a substrate, first and second buses above the first and second active devices, respectively, a bond pad above the first and second buses, first interconnections between the first and second active devices and the bond pad, and second interconnections between the first and second active devices and the first and second buses, respectively. The first active device may be at least one PMOS transistor, and the second active device may be at least one NMOS transistor. A guard band region may be formed in the substrate.

Abstract: A multiple-phase DC—DC converter adds at least one additional phase to an N-phase DC—DC converter to improve the converter's response to changes in load. In one embodiment, an additional phase operates at a switching frequency greater than that of the N phases, to generate a current which is added to the N phase currents to improve the converter's response to changes in load. In another embodiment, an additional phase is configured to improve the converter's response to a load release. Here, the additional phase is kept off during load increase and steady-state conditions. However, when a load release occurs, the additional phase is turned on and acts to extract current from the converter's output terminal while the N phase currents slowly fall, to reduce the magnitude of output voltage overshoot that occurs on load release.