Abstract: A dual voltage switch enables the generation of a pulse which toggles between user-provided first and second voltages (V1 and V2), for which the positive and/or negative slew rates are programmable by means of a user-provided capacitance. A first switch conducts a current I1 between V1 and a common output node in response to a first control voltage, and a second switch conducts a current I2 between V2 and the common output node in response to a second control voltage. A capacitance C is connected to the common output node. A control circuit alternately provides the first and second control voltages such that the common output node is pulled up to V1 at a transfer rate of I1/C when the first control voltage is provided, and pulled down to V2 at a transfer rate of ?I2/C when the second control voltage is provided.

Abstract: Simple, inexpensive, lightweight secondary display systems are provided which extract video data and a direct coupled (DC) voltage from the CardBus slot of a computer. The video data is converted to a video display signal in a video controller and preferably coupled to a head-wearable display (HWD) over an optical fiber. The HWD is powered by the DC voltage which is coupled to it by a metallic conductor bundled with the optical fiber.

Abstract: A single instruction multiple data (SIMD) array cell for processing a data stream, the array including a plurality of cells, each cell having a memory circuit for storing a predetermined region of the data stream; a location register circuit for representing the size and location of the predetermined region of the data stream; a unique identification number; and an arithmetic logic unit responsive to the identification number and a single command common to all cells in a load mode to compute a unique start position for its cell for receiving the predetermined region of the direct memory access data stream. In an execution mode the command word includes an address field applicable to all cells, a data field and an instruction to be performed by the arithmetic logic unit. The arithmetic logic unit in each cell performs the instruction directly on the local value at that address in its memory with the data in the data field.

Abstract: In an optical switching apparatus having a mirror structure bonded to a substrate, the gap between the mirror structure and the substrate is controlled by mechanical standoffs placed between the mirror structure and the substrate. The mirror structure is bonded to the substrate using solder. The mechanical standoffs are formed from a material having a higher melting point than that of the solder. The mirror structure is bonded to the substrate under pressure at a temperature between the melting point of the solder and the melting point of the mechanical standoffs.

Abstract: A drive circuit for a brushless DC motor includes a switch constructed and arranged to drive the motor with a pulse signal responsive to a control signal, and control circuitry coupled to the switch and constructed and arranged to generate the control signal responsive to rotor position information from the motor so as to synchronize the pulse signal to the rotor position. A current sensing device can be used to provide the rotor position information to the control circuitry by sensing current flowing through the motor.

Abstract: A highly-programmable Finite Impulse Response (FIR) digital filter overcomes the limitations of conventional configurations. Specifically, a compound FIR filter configuration is provided, offering the advantages of heightened programmability in both transfer function coefficients hf, hg and in degree of interpolation; distribution and sharing of resources between F and G filter portions, mode-switching capability between high-pass and low-pass modes, and programmable truncation/saturation.

Abstract: A programmable input voltage range analog-to-digital converter in which a split gate oxide process allows the use of high voltage (±15 volt) switches on the same silicon substrate as standard sub-micron 5 volt CMOS devices. With this process, the analog input voltage can be sampled directly onto one or more sampling capacitors without the need for prior attenuation circuits. By only sampling on a given ratio of the sampling capacitors, the analog input can be scaled or attenuated to suit the dynamic range of a subsequent ADC. In the system of the present invention, the sampling capacitor can be the actual capacitive redistribution digital-to-analog converter (CapDAC) used in a SAR ADC itself, or a separate capacitor array. By selecting which bits of the CapDAC or separate sampling array to sample on, one can program the input range.

Abstract: A circuit (1) comprising eight DACs (2a to 2h), the analog outputs of which are applied to the non-inverting inputs (6) of corresponding op-amps (7a to 7h) for gaining up the analog output voltage from the corresponding DAC (2). The op-amps (7) are identical, and are configured in a non-inverting mode with a closed loop gain of two provided by first and second resistors (R1) and (R2). Primary outputs (8) of the op-amps (7) are coupled to output pins (9a to 9h) of the circuit (1). The second resistors (R2) couple primary inverting inputs (12) of the op-amps (7) to a common lo voltage reference rail (14), which is coupled to a true ground reference pin (15) through a coupling wire (16)which exhibit a combined inherent resistance (Rp). The voltage reference on the common voltage reference rail (14) varies with time as the output signals of the pa-amps (7) vary, and would thus result in cross-talk between the DACs (2a to 2h).

Abstract: A MEMS device has at least one conductive path extending from the top facing side of its substrate (having MEMS structure) to the bottom side of the noted substrate. The at least one conductive path extends through the substrate as noted to electrically connect the bottom facing side with the MEMS structure.

Abstract: A DMA controller includes at least one peripheral DMA channel for handling DMA transfers on a peripheral access bus; at least one memory DMA stream, including a memory destination channel and a memory source channel, for handling DMA transfers on first and second memory access buses; first and second address computation units for computing updated memory addresses for DMA transfers; and first and second memory pipelines for supplying memory addresses to the first and second memory access buses, respectively, and for transferring data on the first and second memory access buses. Channel control logic controls transfer of data through the DMA channels in response to parameters contained in at least one DMA descriptor having a programmable format.

Abstract: Methods and apparatus are provided for achieving low latency for high priority tasks in digital processing systems. A digital signal processor includes a core processor and a level one memory. In some embodiments, a store buffer is configured to hold write information for the level one memory and for a level two memory. A write buffer is configured to hold write information, received from the store buffer, for the level two memory. The write buffer has a normal capacity and an excess capacity. A memory controller enables the excess capacity of the write buffer when a high priority task is being serviced and inhibits write access to the excess capacity of the write buffer when a high priority task is not being serviced. In other embodiments, the digital signal processor includes first and second fill buffers configured to hold read data in a fill operation. The memory controller steers low priority read data to the first fill buffer or the second fill buffer based on priority of the fill operation.

Abstract: A circuit and method are provided to enable the synchronization of an on-demand, synchronous signal with an asynchronous signal. The synchronous signal is activate only for a portion of the period of the asynchronous signal, thus providing beneficial power conservation. The synchronous signal is activated in response to a first edge of the asynchronous signal, and deactivated in response to a second edge of the asynchronous signal.

Abstract: Methods and apparatus for handling speculative addresses in a pipelined digital processor are provided. A digital signal processor includes an address generator configured to generate speculative data addresses, a pipelined execution unit configured to execute instructions using data at locations specified by the speculative data addresses, a speculative register file configured to hold the speculative data addresses as corresponding instructions advance through the execution unit, an architectural register file configured to hold architectural data addresses, and control logic configured to write speculative data addresses to the speculative register file as the speculative data addresses are generated by the address generator and to supply speculative data addresses or architectural data addresses to the address generator. The speculative register file may be configured with sufficient capacity to hold one or more architectural data addresses.

Abstract: Methods and apparatus are provided for processing variable width instructions in a pipelined processor. The apparatus includes an instruction decoder configured to decode a loop setup instruction, having a loop setup instruction address, to obtain a loop bottom offset and configured to decode instructions following the loop setup instruction, each having an instruction address, to obtain an instruction width, registers for holding the loop setup instruction address and the loop bottom offset, and a loop bottom detector, responsive to a current instruction address, a current instruction width, the loop setup instruction address and the loop bottom offset, configured to determine if a next instruction is a loop bottom instruction.

Abstract: A DMA controller includes at least one peripheral DMA channel for handling DMA transfers on a peripheral access bus; at least one memory DMA stream, including a memory destination channel and a memory source channel, for handling DMA transfers on first and second memory access buses; first and second address computation units for computing updated memory addresses for DMA transfers; first and second memory pipelines for supplying memory addresses to the first and second memory access buses, respectively, and for transferring data on the first and second memory access buses; and a multiplexer configured to supply first and second current memory addresses to selected ones of the first and second memory pipelines in response to a control signal.

Abstract: A method and apparatus for extending the linear range of a phase detector. In one embodiment, a limited range phase difference is generated between selected edges of first and second input signals, and an excursion of the limited range phase difference beyond a predetermined threshold is detected. In response to detecting the excursion of the limited range phase difference beyond a threshold, an edge of the first or second input signal is prevented from influencing subsequent generation of the limited range phase difference, and a compensated phase difference is generated, derived from the limited range phase difference and including a correction component which compensates for the effect of preventing said edge from influencing subsequent generation of the limited range phase difference.

Abstract: A circuit and method are provided enabling the transfer of signals from a first voltage domain to a second voltage domain. The circuit comprises level shifters enabling the signal transfer, and is space-efficient and power efficient. A 3-wire serial protocol is used to enable the serial transmission of signals across the voltage domain boundary, and provides two distinct reset states.

Abstract: Methods and apparatus for varying and measuring the position of a micromachined electrostatic actuator using a pulse width modulated (PWM) pulse train are disclosed. One or more voltage pulses are applied to the actuator. In each of the pulses, a voltage changes from a first state to a second state and remains in the second state for a time tpulse before returning to the first state. The position of the actuator may be varied by varying the time ?tpulse. A position of the actuator may be determined by measuring a capacitance of the actuator when the voltage changes state, whether the time t is varied or not. An apparatus for varying the position of a MEMS device may include a pulse width modulation generator coupled to the MEMS device an integrator coupled to the MEMS device and an analog-to-digital converter coupled to the integrator. The integrator may measure a charge transferred during a transition of a pulse from the pulse generator.

Abstract: An intermediate electrode layer is used to fabricate an integrated micro-electromechanical system. An intermediate electrode layer is formed on an integrated circuit wafer. The intermediate electrode layer places drive electrodes a predetermined height above the surface of the integrated circuit wafer. A micro-electromechanical system wafer having micromachined optical mirrors is bonded to the integrated circuit wafer such that the drive electrodes are positioned a predetermined distance from the optical mirrors.

Abstract: A fiber-attached optical device with in-plane micromachined mirrors includes a cover having at least one reflector formed on one side and a substrate having a plurality of micromachined optical mirrors formed substantially on a single plane on a side facing toward the mirrored side of the cover. The micromachined optical mirrors are controllable to reflect optical signals between a plurality of optical fiber segments via the at least one reflector. The plurality of optical fiber segments can be attached to either the cover or the substrate so as to form an integrated package including the substrate, the cover, and the plurality of optical fiber segments. The mirrors can be controlled to variably attenuate the optical signals.