Abstract: Methods and structures are provided that reduce conversion errors in pipelined analog-to-digital converters which are induced in one converter cycle by component memory of signals in one or more preceding converter cycles. The methods and structures include the use of digital filters that provide a digital representation of the residue of a preceding converter cycle, multiply this representation by an appropriate memory parameter, and sum the product with the digital representation of the residue of a current converter cycle to thereby reduce the memory effect. The methods and structures also form capacitors of switched-capacitor converter structures with sub-capacitors that are reconfigured (e.g., reversed or alternated between differential sides of differential amplifiers) in different converter cycles.

Abstract: A squaring cell combines first and second exponential currents to approximate square law behavior. The exponential currents can be generated by current stacks having pairs of series-connected junctions. The exponential currents can be altered to change the shape of the exponential currents to better approximation true square law behavior. A multiplier combines four exponential currents to approximate a multiplication function. The exponential currents in the multiplier can be generated by current stacks that are cross-connected so as to generate two output currents, the difference of which represents the multiplication of two input signals.

Abstract: Signal coupling systems are provided which enhance signal isolation and dynamic range with structures that increase bias voltages in upstream signal amplifiers to guard against transistor saturation that would otherwise increase current drain, reduce response time and possibly cause lock-up of an associated gain-control system. Dynamic range is thus enhanced because these systems can operate over an extended range of source signals. The increased bias voltages also decrease parasitic junction capacitances which increases input impedances and thereby enhances signal isolation and reduces signal distortion.

Abstract: A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features for enhanced performance in executing digital signal computations. The computation core is configured for executing digital signal processor instructions and microcontroller instructions, while achieving efficient digital signal processor computation and high code density. A finite impulse response filter algorithm achieves high performance on the dual execution units.

Abstract: A method and apparatus are described for reducing stiction in a MEMS device having a movable element and a substrate. The method generally comprises providing the substrate with an anti-stiction member and interposing the anti-stiction member between the moveable element and the substrate. The apparatus generally comprises an anti-stiction member that is interposable between the moveable element and the substrate. Another embodiment of the invention of the invention is directed to a MEMS device, comprising: a substrate, a moveable element moveably coupled to the substrate, and an anti-stiction member that is interposable between the moveable element and the substrate. A further embodiment of the invention is directed to an optical switch having one or more moveable elements moveably coupled to a substrate, and an anti-stiction member that is interposable between at least one of the moveable elements and the substrate.

Abstract: Switched-capacitor structures are provided that reduce distortion and noise in their processed signals because they increase isolation between structural elements and ensure that selected elements are securely turned off in one mode and quickly turned on in another mode.

Abstract: A method for placing a device in a selected mode of operation. The method comprises the steps of initializing a device select signal into a first logic state, asserting the device select signal in a second logic state, and returning the device select signal to the first logic state within a first user-controlled time window. A device is also described that includes means for detecting logic state transitions at a device select input and a clock input, and means for changing operating mode of the device in response to a predetermined number of logic state transitions at the clock input, occurring between logic state transitions at the device select input. The selected operating mode may be a reduced power consumption mode, for example, or another operating mode of the device, such as a daisy-chain mode of operation, or a mode that accommodates programming of analog input range.

Abstract: A system and method for portable computer battery management using host processing relocates analog and digital components needed to implement the SBDS standard from the battery pack to the computer, which processes the acquired battery data using the host processor. The battery pack requires only battery temperature and voltage sensing circuits, and an interface circuit for conveying the sensed data out of the battery pack. The portable computer includes a circuit which senses current provided to or drawn from the battery. Battery temperature, voltage and current data is provided to the computer's host system, which executes a battery management application program to determine battery status in accordance with the SBDS standard.

Abstract: A plug-in device discrimination circuit is connected to the contacts of a jack. When a plug-in device is plugged into the jack, the circuit discerns the type of device it is, thereby enabling proper interface circuitry to be connected to the plug-in device. The discrimination circuit includes a comparison circuit, a switching network, and a controller. The controller operates the switching network to connect the comparison circuit to the jack contacts. When so connected, the comparison circuit compares the electrical characteristics of at least two of the circuits contained within the plug-in device, and produces an output which varies with the results of the comparison. The controller receives the output of the comparison circuit and may configure additional circuitry to present an appropriate interface to the plug-in device.

Abstract: An oscillator includes a comparator and a variable voltage element. The comparator has a first input set to a reference voltage, a second input, and an output configured to produce an output voltage as a function of the voltages at the first and second inputs. The variable voltage element delivers to the second input a second voltage that is a function of a switched current. The switched current is a function of the reference voltage.

Abstract: The invention describes a bandgap reference circuit that may be configured to provide a reference current or voltage as an output thereof. The output may be provided in the form of a constant source, or one including PTAT or CTAT dependencies. The circuit utilises a single amplifier whose output is coupled to a current control block which is then used to drive a dual feedback loop of the amplifier. Inputs to the amplifier are directly coupled to reference nodes in a manner which establishes a PTAT voltage across a resistor at an input of the amplifier.

Abstract: A communication device is provided which transmits and responds to differential currents. Thereby allowing communication between devices that may be floating with respect to each other.

Abstract: A six degree-of-freedom micro-machined multi-sensor that provides 3-axes of acceleration sensing, and 3-axes of angular rate sensing, in a single multi-sensor device. The six degree-of-freedom multi-sensor device includes a first multi-sensor substructure providing 2-axes of acceleration sensing and 1-axis of angular rate sensing, and a second multi-sensor substructure providing a third axis of acceleration sensing, and second and third axes of angular rate sensing. The first and second multi-sensor substructures are implemented on respective substrates within the six degree-of-freedom multi-sensor device.

Abstract: A voltage selector circuit determines the highest of at least two available input voltages, and connects the highest voltage to an output terminal. The circuit includes a comparator having first and second FETs having their sources connected to first and second input voltages (V1 and V2), and which are biased with first and second bias currents. The first FET is driven on regeneratively when V1>V2, and the second FET is driven on regeneratively when V2>V1. A first switch connects V1 to an output terminal when the first FET is driven on, and a second switch connects V2 to the output terminal when the second FET is driven on. First and second diode-connected FETs are connected below the first and second FETs and carry their respective bias currents, thereby limiting the voltage swings on the FETs' gates and providing control over hysteresis.

Abstract: A micro-machined multi-sensor that provides 2-axes of acceleration sensing and 1-axis of angular rate sensing. The multi-sensor includes a rigid accelerometer frame, a first proof mass, and a second proof mass. The substrate has two associated acceleration axes in the plane of the substrate, and one associated rotation axis perpendicular to the acceleration axes. The proof masses have a common vibration axis, which is perpendicular to the rotation axis. The multi-sensor further includes a drive electrode structure for causing the proof masses to vibrate in antiphase, a first pair of acceleration sense electrode structures disposed along one of the acceleration axes, and a second pair of acceleration sense electrode structures disposed along the other acceleration axis.

Abstract: A wideband impedance attenuator includes a phase-locked loop filter, a voltage-controlled oscillator connected to the phase-locked loop filter during transmit, and an impedance circuit connected to the phase-locked loop filter and the voltage controlled oscillator. The impedance circuit is a scaled version of the phase-locked loop filter. Moreover, the wideband impedance attenuator attenuates a Gaussian frequency shift key modulation signal by a factor of 1/(N+1) using the impedance circuit, which has an impedance of N*Z(s), and the phase-locked loop filter, which has an impedance of Z(s). An output frequency is generated using a voltage-controlled oscillator wherein the output frequency corresponds to the attenuated Gaussian frequency shift key modulation signal. In addition, a comparator compares a voltage of an output from the programmable gain amplifier with a voltage necessary to produce a predetermined frequency shift in a voltage-controlled oscillator to produce a gain signal.

Abstract: In a circuit having two input stages multiplexed to a common output stage having an output, one of the two input stages including transistor having a base, a collector and an emitter; a method of protecting the transistor from ?-degradation when the one of the two input stages is disabled comprises: clamping the base to a substantially fixed voltage for a first range of voltages applied to the one of the two input stages; and bootstrapping the base to a voltage that follows the output for a second range of voltages applied to the one of the two input stages. Alternatively, a method of protecting a transistor having a base connected through a finite impedance to an input voltage, a collector and an emitter, may comprise bootstrapping the base to a voltage that follows the input voltage with an offset when the input voltage is within a second range of voltages.

Abstract: A composite SOI semiconductor wafer (1) comprises a device layer (2) and a handle layer (3) with a buried oxide layer (4) located between the device and handle layers (2,3). The device and handle layers (2,3) are formed from device and handle wafers (9,10), respectively. A peripheral ridge (14) extending around a first major surface (12) of the device wafer (9) adjacent the peripheral edge (16) thereof is removed by etching a peripheral recess (25) to a depth (d) into the device wafer (9) prior to bonding the device and handle wafers (9,10), in order to avoid an unbonded peripheral pardon extending around the composite wafer (1). The depth to which the peripheral recess (25) is etched is greater then the final finished thickness t of the device layer (2). An oxide layer (22) is grown on the device water (9) and a photoresist layer (23) on the oxide layer (22) is patterned to define the peripheral recess (25).

Abstract: A differential variable gain amplifier (1) comprises eight identical variable gain stages (8a to 8d) which are arranged in two groups, namely, a high gain group (19) and a low gain group (20). The first gain stage (8a) is coupled directly to a pair of positive and negative main input terminals (4,5) for receiving a differential input signal to be amplified. A pair of voltage divider impedance chains (14) comprising identical capacitors (C1a to C1g) define taps (17b to 17h) through which the input signal is applied to the corresponding gain stages (8b to 8h) in progressive steps of attenuation. Each gain stage (8) comprises a pair of identical variable gain amplifier elements (11) which amplify the respective positive and negative ends of the differential input signal. Only one of the gain stages (8a to 8h) is selected at any one time by a control circuit 10. The outputs from the gain stages (8) of the high gain group (19) are applied to positive and negative high gain output terminals (28,29).

Abstract: An optical switch (a/k/a “optical switching unit”) includes at least two sides, an input, a plurality of outputs on the same side as the input. The optical switch further includes a plurality of mirrors to direct light beams between the input and at least one of the plurality of outputs. The plurality of mirrors illustratively are pop-up mirrors.