Abstract: Methods and devices for code independent switching in signal processing circuit such as a digital-to-analog converter (DAC) are described, which provide code independent switching activity. A steering cell receives a digital data input signal that is defined at data intervals, and produces multiple representative analog output signals. For each data interval, each analog output signal depends only on the present state of the digital data input signal, independently of any previous state of the digital data input signal. In addition, the signal processing circuit apart from the analog output signals is substantially free of data dependent disturbances.

Abstract: A two input, two output optical switch includes two movable mirrors. Each movable mirror is used for two optical signal reflections, one from an input fiber collimator to the same or a different movable mirror via a fixed cover mirror, and one from the same or a different movable mirror via the fixed cover mirror to an output fiber collimator. A single electrode may be used to control the mirror positions.

Abstract: The present invention provides an improved reference source. The reference source has reduced sensitivity to the input offset voltage of the amplifier components in the reference circuit. This is achieved by subtracting two currents at the reference output node such that the combined offset sensitivity is less than the corresponding offset sensitivity for only one current.

Abstract: An emulator couplable to an integrated circuit, the integrated circuit including a micro controller, a DMA controller, memory means and an ADC and the emulator being operable to read a block of data stored in a plurality of memory locations of the memory means and graphically to display a representation of at least a portion of the block of data. An integrated circuit including an ADC and reprogrammable non-volatile memory means, the ADC being arranged to read calibration values from the non-volatile memory means. An integrated circuit including a microcontroller, a DAC selected from a group consisting of a string DAC and a current source DAC and an operational amplifier coupled to the DAC output. An integrated circuit includes analog and digital circuitry, and has only two polysilicon layers on a C-MOS substrate.

Abstract: A micro-machined multi-sensor that provides 1-axis of acceleration sensing and 2-axes of angular rate sensing. The multi-sensor includes a plurality of accelerometers, each including a mass anchored to and suspended over a substrate by a plurality of flexures. Each accelerometer further includes acceleration sense electrode structures disposed along lateral and longitudinal axes of the respective mass. The multi-sensor includes a fork member coupling the masses to allow relative antiphase movement, and to resist in phase movement, of the masses, and a drive electrode structure for rotationally vibrating the masses in antiphase. The multi-sensor provides electrically independent acceleration sense signals along the lateral and longitudinal axes of the respective masses, which are added and/or subtracted to obtain 1-axis of acceleration sensing and 2-axes of angular rate sensing.

Abstract: Methods and structures are provided for the interleaved calibration and subsequent correction of errors in switched-capacitor converter stages of pipelined analog-to-digital converters. The interleaved calibration can be run continuously or at selected times without disturbing the ongoing processing of input data signals. With first and second sets of capacitors, converter stages interleavably process input data signals and input calibration signals. Once these stages have been calibrated with their second sets of capacitors, the first and second sets are exchanged and the converter stages subsequently process input data signals with their second sets of capacitors.

Abstract: A method for forming an LDNMOS (1) and LDPMOS (2) in a CMOS process comprises forming the LDNMOS (1) and LDPMOS (2) to a stage where a gate (14) is laid down on a gate oxide layer (12) and a locos (9) is formed over the respective N and P-wells (4) and (5) of the LDNMOS (1) and LDPMOS (2). A P-body (15) is formed in the N-well (4) of the LDNMOS (1) by implanting a boron dopant in two stages, in the first stage at a first tilt angle (&thgr;) of 45° for forming the P-body (15) beneath the gate (14) for determining the source/drain threshold voltage, and subsequently at a second tilt angle (&phgr;) of 7° for extending the P-body (15) downwardly at (25) for determining the punchthrough breakdown voltage of the LDNMOS (1). The formation of an N-body (16) in a P-well (5) of the LDPMOS (2) is similar to the formation of the P-body (15) with the exception that the dopant is a phosphorous dopant.

Abstract: Comparator systems are provided that substantially enhance comparator dynamic range. The enhancement is primarily realized by arranging the systems to apply comparator input signals at feedback taps positioned between the upper and lower ends of comparator strings of impedance elements.

Abstract: An optical mirror module has an interface port that is spaced from a corresponding die. More specifically, the optical mirror module includes a substrate and a die having at least one mirror and circuitry to control the at least one mirror. The optical mirror module defines a plane that is substantially parallel to the die. The optical mirror module further includes the noted interface port, which is adapted to electrically couple the circuitry with a device external to the optical mirror module. As suggested above, the interface port is located on the substrate and spaced from the die on the plane.

Abstract: Latch structures and systems are disclosed that enhance latch speed and provide complementary metal-oxide-semiconductor (CMOS)-level latch signals. They are realized with bipolar junction structures and CMOS structures that are arranged to enhance regenerative feedback signals and generate CMOS-level latch signals.

Abstract: An integrated circuit (1) comprises a microprocessor (2), an ADC (3) and a serial interface (4) for communicating the integrated circuit with an external device. An analogue input port (5) is provided for inputting analogue signals to the ADC (3). A switch circuit (8) is provided for selectively and alternately configuring the integrated circuit (1) to operate in a first mode and in a second mode. In the first mode the serial interface (4) communicates with the microprocessor (2) through the switch circuit (8), and in the second mode the serial interface (4) communicates with the ADC (3) through the switch circuit (8). In the second mode conversion results are transferred from the ADC (3) through the switch circuit (8) to the serial interface (4) independently of the microprocessor (2) for transmission therefrom to an external device. In the first mode the ADC (3) is operable under the control of the microprocessor (2).

Abstract: A bandgap voltage reference circuit (1) comprises a bandgap cell (7) comprising first and second transistor stacks (8,9) of first transistors (Q1,Q2) and second transistors (Q3,Q4), respectively, arranged for developing a correcting PTAT voltage (&Dgr;Vbe) across a primary resistor (R1) proportional to the difference in the base-emitter voltages of the first and second transistor stacks (8,9). A first current mirror circuit (10) provides PTAT currents (12 to 15) to the emitters of the first and second transistors (Q1 to Q4), and an operational amplifier (A1) maintains the voltage on the emitter of the first transistor (Q2) of the first transistor stack (8) at the same level as the resistor (R1) and sinks a PTAT current from the first current mirror circuit (10) from which the other PTAT currents are mirrored.

Abstract: A hermetically sealed wafer scale package for micro-electrical-mechanical systems devices. The package consists of a substrate wafer which contains a microstructure and a cap wafer which contains other circuitry and electrical connectors to connect to external applications. The wafers are bonded together, and the microstructure sealed, with a sealant, which in the preferred embodiment is frit glass. The wafers are electrically connected by a wire bond, which is protected by an overmold. Electrical connectors are applied to the cap wafer, which are electrically linked to the outputs and inputs of the microstructure. The final package is small, easy to manufacture and test, and more cost efficient than current hermetically sealed microstructure packages.

Abstract: A SAR converter having enhanced performance by virtue of effectively pre-loading the SAR's most significant bits with a value that makes the associated DAC output almost equal to the signal to be converted. A normal SAR conversion is then completed with the SAR bits that have not been pre-loaded. The value used to pre-load the most significant bits of the SAR is preferably obtained from a low-resolution, high-speed converter, such as a flash. The range of DAC bits used in the normal SAR part of the conversion may be increased such that errors up to a certain magnitude in the high-speed converter can be corrected. A method for performing an enhanced SAR conversion is also described.

Abstract: A reconfigurable parallel look-up table system includes a memory; a plurality of look-up tables stored in the memory; a row index register for holding the values to be looked up in the look-up tables; a column index register for storing a value representing the starting address of the look-up tables stored in the memory; and an address translation circuit responsive to the column index register and the row index register to simultaneously generate an address for each value in the row index register to locate in parallel the function of those values in each look-up table.

Abstract: In one embodiment, a watchpoint engine generates watchpoints for code developed for a complex integrated circuit device such as a pipelined processor.

Abstract: A microwave directional coupler includes a first transmission line having an input port and an output port, and a second transmission line having a coupled port and a terminated port. The second transmission line is electromagnetically coupled to the first transmission line. A first capacitor is coupled between the input port and a reference potential, such as ground, a second capacitor is coupled between the output port and the reference potential, a third capacitor is coupled between the coupled port and the reference potential, a fourth capacitor is coupled between the terminated port and the reference potential, and a fifth capacitor is coupled between the output port and the terminated port. The microwave directional coupler has a small size in comparison with prior art directional couplers.

Abstract: A microstructure package and a method of assembling such a package are described. A package base provides an outer body of the package and has an internal cavity. A device die is located within the cavity, and a flexible die paddle connects the base and the die. The paddle is immovably fixed to hold the die in a highly precise position relative to the base.

Abstract: An instruction alignment unit for aligning instructions in a digital processor having a pipelined architecture includes an instruction queue, a current instruction buffer and a next instruction buffer in a pipeline stage n, an aligned instruction buffer in a pipeline stage n+1, instruction fetch logic for loading instructions into the current instruction buffer from an instruction cache or from the next instruction buffer and for loading instructions into the next instruction buffer from the instruction cache or from the instruction queue, and alignment control logic responsive to instruction length information contained in the instructions for controlling transfer of instructions from the current instruction buffer and the next instruction buffer to the aligned instruction buffer.

Abstract: In a circuit having two input stages multiplexed to a common output stage having an output, one of the two input stages including transistor having a base, a collector and an emitter; a method of protecting the transistor from &bgr;-degradation when the one of the two input stages is disabled comprises: clamping the base to a substantially fixed voltage for a first range of voltages applied to the one of the two input stages; and bootstrapping the base to a voltage that follows the output for a second range of voltages applied to the one of the two input stages. Alternatively, a method of protecting a transistor having a base connected through a finite impedance to an input voltage, a collector and an emitter, may comprise bootstrapping the base to a voltage that follows the input voltage with an offset when the input voltage is within a second range of voltages.