Abstract: An invalid reference detection circuit formed on a semiconductor chip having: reference input terminals adapted for coupling to a reference source external to the chip; a local reference source; and comparison circuit. The comparison circuit is responsive to the local reference source and a condition at the reference input terminals to detect an invalid condition at the reference input terminals and to produce an output signal indicative of the detected invalid condition. The invalid condition at the reference input terminals may be an open circuit condition at at least one of the reference input terminals, a condition when the voltage across the reference input terminals is below a predetermined minimum voltage level, a condition when the voltage across the reference input terminals is above a predetermined maximum voltage level, and/or a short circuit condition. An analog/digital conversion system is formed on a semiconductor chip together with the invalid reference detection circuit.

Abstract: An integrated circuit chip is provided having an electrical circuit formed therein. A plurality of devices is formed in an active device region of the chip, such devices being connected as active devices. A plurality of additional ones such device are formed in a region adjacent to the active device region, such additional ones of the devices being connected as passive devices. The additional devices provide a dual purpose: first there presence improves the electrical characteristic matching among the devices which are to provide the active devices for the circuit; and, second, they are available to provide passive devices for use by the circuit rather then merely taking up space as a mere "dummy" previously unused by the circuit. More particularly, a plurality of first devices is formed in an active device region of the chip to provide the active devices. Each one of such first devices has the same shape and size.

Abstract: A leadframe that exhibits improved thermal dissipation and that can be incorporated in standard integrated circuit (IC) package designs is provided by extending the inner lead portions along a major surface of an IC, and attaching a heat sink on a side of the inner lead portions opposite the IC. The inner lead portions conduct heat from the IC to the heat sink, where it is dissipated into the moulding compound and radiated into the air. In the preferred embodiment, the leads have outer portions that are arranged on only two opposing sides of the IC package and comprise four sets of leads that initially intersect the IC along four lateral sides. This allows for a larger number of leads to contribute to heat dissipation. Added thermal dissipation is achieved by making the inner portion of a ground lead wider than the inner portion of any other lead.

Abstract: A composite load circuit for use within another circuit includes at least one amplifying transistor. The composite load circuit includes first and second transistors connected in parallel. Each load transistor has a gate that receives a common control voltage. Each load transistor also has a different turn-on threshold voltage. A resistor, connected in parallel with the load transistors, limits an effective impedance of the load transistors.

Abstract: A method of identifying the non-clustered failure yield on a wafer which includes: measuring an absolute yield of the chips on a wafer; identifying a first set of clustered failed chips in which each failed chip is disposed in a field of chips whose yield is below the absolute yield; determining an adjusted yield discounted for the first set of clustered failed chips; identifying at least one additional set of clustered failed chips in which each failed chip is disposed in a field of chips whose yield is below the adjusted yield; and determining an additional adjusted yield for each additional set of clustered failed chips discounting for the previous set of clustered failed chips until the difference between the additional adjusted yield and the previous adjusted yield are within a predetermined maximum acceptable difference for indicating a non-clustered failure yield of the wafer.

Abstract: A high-gain, low-power transconductance amplifier suitable for use in switched-capacitor circuits provides improved accuracy and high-speed operation. The transconductance amplifier includes an input circuit that receives an input voltage. A current mirror circuit is coupled to the input circuit. At least one active cascode circuit, coupled to the current mirror circuit, receives current from the current mirror circuit and provides an output current. The active cascode circuit provides gain enhancement to the transconductance amplifier by increasing the output impedance of the transconductance amplifier.

Abstract: The dc-offset voltage of an amplifier is calibrated by: (1) configuring the amplifier as a comparator, (2) using the output of the comparator to drive the up/down select input of an up/down counter, and (3) using the output count of the up/down counter to control: (a) a dc-offset correction voltage being: (i) applied across the inputs of the amplifier, or (ii) being used to adjust a voltage which controls an operating parameter of a device in the amplifier, or (b) switches which selectively adjust the effective size or operating conditions of a transistor or other device such that the dc-offset voltage of the amplifier is adjusted corresponding to the value of the output count.

Abstract: A multi-phase, multi-access pipeline memory system includes a number, n, of processors; a pipeline memory including a latch; and a bus for interconnecting the processors and pipeline memory; a clock circuit responsive to a system clock signal divides the system clock signal into n phases for providing multiple clock signals corresponding to the n phases of the system clock signal for application to each processor to allow data and address to be transferred only during its assigned phase thereby enabling the memory and each processor to operate at the system clock rate while allowing n accesses to the memory during each system clock signal period, one access for each processor.

Abstract: A digital oversampling noise-shaping system includes a digital noise-shaped clock signal generating circuit, including a DCO operating at a fixed master clock rate, that receives a digital input sample clock signal having an input sample rate and produces a noise-shaped clock signal having a variable rate with an average rate equal to a multiple of the input sample rate. In one embodiment, an interpolator is coupled to the clock signal generating circuit and receives the digital input samples at an input sample rate and, responsive to the noise-shaped clock signal, upsamples the digital input samples at the variable rate. A hold circuit repeats the interpolated samples at the master clock rate. A digital noise-shaping circuit, coupled to the hold circuit, performs digital noise-shaping on the repeated samples received from the hold circuit. In another embodiment, a decimator is coupled to the clock signal generating circuit.

Abstract: A switched capacitance phase locked loop (PLL) system includes a filter circuit having a scaling channel for scaling the phase error; an integrating channel for integrating the phase error; and a summing device for combining the scaled phase error and the integrated phase error; a voltage controlled oscillator (VCO) responsive to the summing device produces an output; the VCO's gain is proportional to its output clock frequency; the integrating channel includes a switched capacitance integrating circuit for controlling the gain of the integrating channel proportional to the output clock frequency of the VCO and maintaining constant the ratio of, and scaling the product of, the unity gain frequency and the zero frequency of the phase locked loop to keep constant the damping factor and to scale the natural frequency of the phase locked loop with the output clock frequency of the VCO, respectively.

Abstract: A video decoder is provided wherein digitized samples of an input video signal are produced at a fixed sampling rate and, from such digitized samples, a fixed number of re-sampled digitized samples are produced for each detected sync pulse included in the video signal. The re-sampled digitized samples are stored in a buffer memory and are retrieved from such buffer memory at a rate synchronized to the sync pulse. With such an arrangement, the analog to digital converter operates at a fixed sampling rate, and overflow situations are avoided.

Abstract: A novel finite impulse response filter apparatus and method. A multiplexed data stream composed of two or more data streams is provided as an input to a tapped delay line. Weight and sum operators are connected to the even or odd delay line taps and generate a filtered output. The filter operates on one data stream per cycle and generates a multiplexed output. In another form, odd weight and sum operates are connected to and odd taps generating two filtered outputs. The filter operates on both data streams in each cycle and generates two multiplexed outputs. A crossbar switch is disclosed for parsing the multiplexed outputs into the constituent filtered data streams. The filter stages may be cascaded.

Abstract: A digital filtering system is fed by input signal and produces an output signal from either a relatively low bandwidth filter or a relatively wide bandwidth filter selectively in accordance with the time rate of change in the input signal. The output signal is produced by the relatively low bandwidth filter when the input signal is slowly varying and the output signal is produced by the relatively wide bandwidth filter when the input signal changes rapidly, after which the output is produced from the relatively low bandwidth filter when the input signal reverts to its more slowly varying characteristics.

Abstract: A circuit for use with a magnetic sensing device having at least first and second sensors has a summing amplifier for providing a difference signal and a peak detector for detecting peaks in the difference signal. The peaks determine a spatial offset of a transition in a sensed body.

Abstract: A data transmission system wherein a datastream of digital words is processed in two parallel pipelined datapaths with the logical operations being performed at a clock rate which is a fraction of some other clock rate identified as a main clock rate. The outputs of the datapath logic are directed respectively to T-latch storage registers the outputs of which are directed at the fractional clock rate to corresponding inputs of a multiplexer serving to combine the two datastreams into a single datastream at the main clock rate. The multiplexer is clocked in synchronism with the T-latch clocks in timed sequence to prevent the development of a transparent path between either T-latch input and the multiplexer output.

Abstract: Operational transconductance amplifiers (OTAs) are combined at their outputs, yielding a single frequency compensation connection point. In a preferred embodiment, the output of each OTA is asymmetric, i.e., they can only source current and the OTA outputs are tied together to a constant current sink. Consequently, the OTA that sources more current controls the voltage of the merged output. This merged output point provides a voltage output that may be used as a frequency compensation point.

Abstract: An integrated circuit chip for determining when the frequency of a clock pulse input signal is below a predetermined threshold level and including a capacitor charged up by a current source to produce a linearly-varying ramp signal. The charging circuit includes two MOS transistors, one arranged as a resistor to control the charging current, the other arranged as a capacitor to be charged. When the oxide layer produced by the IC process for making the chips varies in thickness from one batch of chips to a subsequently produced batch, the effect on the charging of the MOS capacitor resulting from the change in capacitance of the previously produced chip is at least partly compensated for by the corresponding change in resistance of the MOS resistor, thereby tending to maintain the charging rate constant.

Abstract: A CMOS layout enables the matching of an intentionally created parasitic capacitance to an existing parasitic capacitance, for example, a gate-to-drain capacitance of a MOSFET, with a high degree of precision. This precise matching allows a differential pair of MOSFETs acting as the input of an amplfier to have intentionally created capacitances (that match the parasitic gate-to-drain capacitances) cross-coupled between the inputs and the outputs of the differential pair. This cross-coupling of matching capacitances effectively cancels the bandwidth reducing effect of the gate-to-drain capacitances of the differential pair. The layout provides for the interdigitation of the gates of the differential pair, with each input transistor comprising at least two transistors connected together to form a single input transistor.

Abstract: A read system for implementing PR4 and higher order PRML signals includes: a continuous time programmable filter, for receiving a read signal representative of a binary signal from a storage medium and for shaping the read signal into a PR4 shaped read signal; an analog finite impulse response (AFIR) filter, responsive to the continuous time programmable filter, for sampling and forming the PR4 shaped read signal into a PR4 shaped multilevel read signal; an analog to digital converter, responsive to the AFIR filter, for converting the PR4 shaped multilevel read signal from analog to digital; a data sequence filter, responsive to the analog to digital converter, for transforming the PR4 shaped multilevel digital read signal to a predetermined order PRML signal; and a Viterbi detector, responsive to the data sequence filter, for detecting the binary signal from the predetermined order PRML signal.

Abstract: A switch architecture for a digital-to-analog converter provides improved linearity. A first switch for one leg of the R/2R resistance ladder includes a unit resistor coupled between the MOSFET devices of the switch and the respective leg of the R/2R ladder. The on resistances of the MOSFET devices of the first switch are controlled in response to a reference value, such as the resistance of a reference resistor, which may have a resistance and other characteristics similar to the unit resistor. Other switches for other legs of the R/2R ladder also have a unit resistor, or other MOSFET devices having an on resistance controlled in relation to the reference value. Additional switches for other legs of the R/2R ladder may also have MOSFET devices of varying width to channel (W/L) ratios. Each of these approaches may be combined to achieve a binary weighting or an alternate weighting between legs of the R/2R ladder, in order to provide low linearity error.