Abstract: An ESD protection circuit allows a certain level of ESD current to flow through a protected circuit, and actuates a bypass path for greater ESD current levels when the sensed current reaches a threshold level. For a protected circuit having a pair of differential input terminals and a reference voltage terminal, the bypass path is provided between an input terminal which receives an ESD and the reference voltage terminal when the reference voltage is fixed, and between the two input terminals when the reference voltage is floating. The bypass circuit is preferably implemented with a pair of bipolar transistors of a first conductivity that are actuated by an ESD current flow through the protected circuit, and a pair of bipolar transistors of opposite conductivity that are actuated by current flows through the first conductivity transistors.

Abstract: An apparatus and a method for multiplying two time varying signals to produce a four quadrant, multiplied signal is provided. In one embodiment of the present invention, an apparatus for multiplying a first signal with a second signal includes an analog-to-digital converter that provides a first digital signal representative of the first signal, a first modulator that provides a first modulated signal representative of the second signal, a multiplier that multiplies the first digital signal by the first modulated signal and provides a second digital signal representative of a result of a multiplication of the first signal and the second signal, and a first filter having an input to receive the second digital signal and having an output that provides the multiplied signal.

Abstract: A clock-to-clock auto-ranging ADC operates directly on an analog signal in the IF band or higher to track its gain range on a clock-to-clock basis and produce a digital signal that maintains high resolution of the analog signal without clipping or loss of signal sensitivity. This is accomplished by sampling an analog signal of sufficiently high frequency that a peak detector can accurately determine the maximum signal level over at least one-half a signal period and then reset the signal gain going into the ADC prior to the beginning of the next sampling period. This insures that the analog signal will always be within the range of the ADC. In accordance with the well known principles of sampling theory, the sampled analog signal is aliased into the frequency region between DC and one half the sampling frequency.

Abstract: A method and apparatus for providing a conductive plane beneath a suspended microstructure. A conductive region is diffused into a substrate. A dielectric layer is added, covering the substrate, and then removed from a portion of the conductive region. A spacer layer is deposited over the dielectric and exposed conductive region. A polysilicon layer is deposited over the spacer layer, and formed into the shape of the suspended microstructure. After removal of the spacer layer, the suspended microstructure is left free to move above an exposed conductive plane. The conductive plane is driven to the same potential as the microstructure.

Abstract: A reference buffer suitable for driving switched-capacitor or resistive load circuits provides a very low output impedance. The reference buffer utilizes an amplifier with a very large and controlled transconductance configured in feedback and compensated by a load capacitance. Cascaded gain stages are used to provide a large, controlled transconductance. In one embodiment, a reference buffer amplifier includes a plurality of voltage gain amplifiers connected in cascade and at least one transconductance amplifier connected to a last-connected of the plurality of voltage gain amplifiers. The amplifier may further include at least one current mirror amplifier connected to the at least one transconductance amplifier. In another embodiment, the reference buffer amplifier includes at least one transconductance amplifier and at least one current mirror amplifier cascade-connected to the at least one transconductance amplifier. The amplifiers can be differential or single-ended.

Abstract: A charge redistribution analog-to-digital converter. This converter includes an offset correcting circuit operatively connected in parallel with a capacitor array and responsive to a sampling input of the analog-to-digital converter, and a gain correcting circuit operatively connected in parallel with a sampling capacitor and responsive to the sampling input of the analog-to-digital converter. In another general aspect, an analog-to-digital converter calibration method for a charge redistribution analog-to-digital converter, that includes adjusting an input offset of an input of the analog-to-digital converter and adjusting a gain offset of the analog-to-digital converter. The steps of adjusting are then repeated until a predetermined level of error is achieved for the analog-to-digital converter.

Abstract: An all npn totem pole TTL output stage is provided with an active regulation circuit that continuously senses the voltage level at the output terminal and feeds it back to control the drive signal that is applied to the base of the bottom output transistor to switch the output state of the load quickly without wasting transient current and then scale back the drive signal during steady state operation to minimize wasted current. When the load is driven into its output low state, the active regulation initially holds the drive signal at a high level so that the load switches quickly. Once the output voltage has fallen low enough, the active regulation reduces the drive signal such that the bottom output transistor is held on the edge of conduction and does not saturate. In this state, the bottom output transistor pulls the output voltage down to approximately ground without conducting any appreciable amount of current.

Abstract: A two-stage switched-capacitor residue amplifier having novel circuitry in the first and second stages provides fast and accurate settling while configured with a large closed-loop gain, and also provides low power consumption while powered from a five volt supply. The invention is particularly well suited for use in a multi-stage, pipe-lined analog-to-digital converter (ADC) that converts multiple bits in the first pipeline stage. Complementary PMOS and NMOS differential pairs are used in the first and/or second stage to increase the current slew capability of the amplifier. Current mirror gain and/or positive feedback is used in the second stage to increase transonductance and bandwidth. Cascode transistors are used in the output of the first and/or second stages and active cascode gain enhancement is used in the first stage to increase dc gain and accuracy.

Abstract: A monolithic capacitance-type microstructure includes a semiconductor substrate, a plurality of posts extending from the surface of the substrate, a bridge suspended from the posts, and an electrically-conductive, substantially stationary element anchored to the substrate. The bridge includes an element that is laterally movable with respect to the surface of the substrate. The substantially stationary element is positioned relative to the laterally movable element such that the laterally movable element and the substantially stationary element form a capacitor. Circuitry may be disposed on the substrate and operationally coupled to the movable element and the substantially stationary element for processing a signal based on a relative positioning of the movable element and the substantially stationary element. A method for fabricating the microstructure and the circuitry is disclosed.

Abstract: A charge pump in a phase locked loop is enabled only when a loop filter needs to be updated, thereby reducing the power consumption of the charge pump. The charge pump is enabled or disabled in response to an enable signal which is generated by a latch. The enable signal is activated by look-ahead signals which are activated in advance of either a pulse from a reference signal or a pulse from a variable signal so as to allow the charge pump to stabilize before providing the charge current to update the loop filter. Logic signals from a programmable divider and reference signal generator are used to generate the look-ahead signals. The charge pump is disabled by a reset signal from a phase-frequency detector after the loop filter is updated. The charge pump includes a current switch for generating source and sink charge currents in response to pump-up and pump-down control signals. A bias cell provides two reference signals to the current switch.

Abstract: A digital-to-analog video encoder method and apparatus having unique equalization are disclosed. The encoder converts digital video signals into one or more analog video formats using one or more digital-to-analog converters. Equalization is provided to compensate for zero order hold effects of the digital-to-analog converters. Equalization is provided to a luminance signal and/or a chroma signal to equalize RGB, composite video, and super VHS video outputs. Multiplexed digital-to-analog converter inputs allow selection of several output formats.

Abstract: A digital signal processor for a PRML system includes: an NMOS pass transistors gain control circuit responsive to a digital data signal for adjusting the gain of the digital data signal; an NMOS pass transistor phase control circuit responsive to the digital data signal for adjusting the phase of the data signal; and an NMOS pass transistor Viterbi maximum likelihood detector circuit for determining the most probable sequence of symbols in the data signal.

Abstract: A video compression circuit comprises an input that receives an input video signal. A memory buffer, coupled to the input, temporarily stores a portion of the input video signal. A single horizontal filter bank, coupled to the memory buffer, high-pass and low-pass filters horizontal components of the input video signal. A single vertical filter bank, also coupled to the memory buffer, high-pass and low-pass filters vertical components of the input video signal. A recursion buffer, coupled to the filter banks, temporarily stores filter components of the input video signal for recursive filtering.

Abstract: Gain correction for a digital filter is accomplished by multiplying each data value by a coefficient representing the impulse response of the filter to form a convolution of the data values; accumulating the sum of the product of each multiplication to obtain a complete convolution; determining the difference between the positive full scale output and the negative full scale output of the filter; combining this difference with the ideal full scale output value to obtain the gain error factor; dividing the gain error factor by the full scale ideal value to obtain the gain correction factor; multiplying the negated accumulated sum of the product of each multiplication by the gain correction factor to obtain the gain error adjustment factor and combining the gain error adjustment factor with the accumulated sum to compensate for gain errors in the filter output.

Abstract: An apparatus and method for providing EOS/ESD protection against an EOS/ESD event across first and second pads of an integrated circuit. In one embodiment, the EOS/ESD protection circuit includes an NMOS device having a drain and source respectively coupled to the first and second pads of the integrated circuit, a capacitor coupled between the drain and gate of the NMOS device and a clamping circuit coupled between the gate and the source of the NMOS device to maintain a voltage at the gate less than or equal to a clamping voltage of the clamping circuit. In embodiments of the present invention, the protection circuit includes an active pull down circuit for reducing the voltage across the gate and source of the NMOS device to zero volts a predetermined period of time after the EOS/ESD event, and the protection circuit further includes a current source for providing bias current to the clamping circuit.

Abstract: A two-stage switched-capacitor CMOS Miller-compensated amplifier uses only n-channel transistors in its signal path to reduce the deleterious effects of parasitic capacitances in the signal path while still obtaining a high transconductance in both stages. A transistor inserted in series with the Miller capacitor between the output and input of the second stage of the amplifier introduces a feedforward zero in the left half of the S-plane of the circuit. By appropriately sizing the aspect ratio and properly biasing this transistor, the second pole of the amplifier is canceled with the introduced zero. Dummy transistors having their sources and drains connected (to serve as capacitors) are cross-connected between opposite polarity inputs and outputs of a differential pair of input transistors in the first stage to effectively cancel the gate-to-drain Miller-multiplied capacitance of the input transistors.

Abstract: A JFET pair having unequal pinchoff voltages is operated in saturation with equal source-drain current to channel width-to-length ratios to provide a reference voltage output. Positive or negative voltage references can be implemented using either n-channel or p-channel JFETs. The pinchoff voltage difference results from the channel for one JFET having a heavier doping level than that of the other JFET.

Abstract: A polysilicon ground plane is formed over dielectric layers and under a suspended, movable mass in a surface micromachined device. The process includes steps of forming a diffused region in a substrate, forming the dielectric layers over the substrate, forming the ground plane over dielectric layers, and forming a body having a suspended mass, a first anchor extending from the mass down to the diffused region, and a second anchor extending from the down to the ground plane. The two anchors are formed simultaneously. The ground plane, which can be formed with only three additional steps over prior processes, serves as a ground plane to control changes and also as a local interconnect.

Abstract: A mixer includes a doubly-balanced mixer core, an RF input section coupled to the mixer core, and a biasing circuit coupled to the RF input section. The RF input section includes a first transistor coupled to a first input of the mixer core for supplying a first current thereto. The base of the first transistor is driven by an RF input current, as a result, the first current is responsive to the RF input current. The RF input section also includes a current mirror coupled to the first transistor, which mirrors the sum of the first current and the RF input current to produce a second current that is complementary to the first current for small variations of the RF input current. The current mirror is coupled to a second input of the mixer core to supply the second current thereto. A biasing circuit is coupled to the RF input section to establish a quiescent value of the first current. Padding resistor can also be used in the RF input section to provide a predetermined input impedance to the RF input current.

Abstract: A band-gap voltage reference forming part of a CMOS IC chip. A .DELTA.V.sub.BE voltage is developed by stacked pairs of parasitic bipolar transistors, with the transistors of each pair operated at different current densities. MOS buffer transistors are connected at corresponding ends of the stacks where the .DELTA.V.sub.BE voltage is developed. The bipolar transistors are driven by MOS current sources.