Abstract: A digital filtering system is fed by input signal and produces an output signal from either a relatively low bandwidth filter or a relatively wide bandwidth filter selectively in accordance with the time rate of change in the input signal. The output signal is produced by the relatively low bandwidth filter when the input signal is slowly varying and the output signal is produced by the relatively wide bandwidth filter when the input signal changes rapidly, after which the output is produced from the relatively low bandwidth filter when the input signal reverts to its more slowly varying characteristics.

Abstract: A circuit for use with a magnetic sensing device having at least first and second sensors has a summing amplifier for providing a difference signal and a peak detector for detecting peaks in the difference signal. The peaks determine a spatial offset of a transition in a sensed body.

Abstract: A data transmission system wherein a datastream of digital words is processed in two parallel pipelined datapaths with the logical operations being performed at a clock rate which is a fraction of some other clock rate identified as a main clock rate. The outputs of the datapath logic are directed respectively to T-latch storage registers the outputs of which are directed at the fractional clock rate to corresponding inputs of a multiplexer serving to combine the two datastreams into a single datastream at the main clock rate. The multiplexer is clocked in synchronism with the T-latch clocks in timed sequence to prevent the development of a transparent path between either T-latch input and the multiplexer output.

Abstract: Operational transconductance amplifiers (OTAs) are combined at their outputs, yielding a single frequency compensation connection point. In a preferred embodiment, the output of each OTA is asymmetric, i.e., they can only source current and the OTA outputs are tied together to a constant current sink. Consequently, the OTA that sources more current controls the voltage of the merged output. This merged output point provides a voltage output that may be used as a frequency compensation point.

Abstract: An integrated circuit chip for determining when the frequency of a clock pulse input signal is below a predetermined threshold level and including a capacitor charged up by a current source to produce a linearly-varying ramp signal. The charging circuit includes two MOS transistors, one arranged as a resistor to control the charging current, the other arranged as a capacitor to be charged. When the oxide layer produced by the IC process for making the chips varies in thickness from one batch of chips to a subsequently produced batch, the effect on the charging of the MOS capacitor resulting from the change in capacitance of the previously produced chip is at least partly compensated for by the corresponding change in resistance of the MOS resistor, thereby tending to maintain the charging rate constant.

Abstract: A read system for implementing PR4 and higher order PRML signals includes: a continuous time programmable filter, for receiving a read signal representative of a binary signal from a storage medium and for shaping the read signal into a PR4 shaped read signal; an analog finite impulse response (AFIR) filter, responsive to the continuous time programmable filter, for sampling and forming the PR4 shaped read signal into a PR4 shaped multilevel read signal; an analog to digital converter, responsive to the AFIR filter, for converting the PR4 shaped multilevel read signal from analog to digital; a data sequence filter, responsive to the analog to digital converter, for transforming the PR4 shaped multilevel digital read signal to a predetermined order PRML signal; and a Viterbi detector, responsive to the data sequence filter, for detecting the binary signal from the predetermined order PRML signal.

Abstract: A CMOS layout enables the matching of an intentionally created parasitic capacitance to an existing parasitic capacitance, for example, a gate-to-drain capacitance of a MOSFET, with a high degree of precision. This precise matching allows a differential pair of MOSFETs acting as the input of an amplfier to have intentionally created capacitances (that match the parasitic gate-to-drain capacitances) cross-coupled between the inputs and the outputs of the differential pair. This cross-coupling of matching capacitances effectively cancels the bandwidth reducing effect of the gate-to-drain capacitances of the differential pair. The layout provides for the interdigitation of the gates of the differential pair, with each input transistor comprising at least two transistors connected together to form a single input transistor.

Abstract: A switch architecture for a digital-to-analog converter provides improved linearity. A first switch for one leg of the R/2R resistance ladder includes a unit resistor coupled between the MOSFET devices of the switch and the respective leg of the R/2R ladder. The on resistances of the MOSFET devices of the first switch are controlled in response to a reference value, such as the resistance of a reference resistor, which may have a resistance and other characteristics similar to the unit resistor. Other switches for other legs of the R/2R ladder also have a unit resistor, or other MOSFET devices having an on resistance controlled in relation to the reference value. Additional switches for other legs of the R/2R ladder may also have MOSFET devices of varying width to channel (W/L) ratios. Each of these approaches may be combined to achieve a binary weighting or an alternate weighting between legs of the R/2R ladder, in order to provide low linearity error.

Abstract: An insubstantial amount of noise results at the output of a circuit when an output of a primary amplifier is disconnected from and reconnected to the circuit in which is operating. The primary amplifier is placed temporarily in a muting configuration. A secondary amplifier permanently in a muting configuration is connected in parallel with the primary amplifier. The output of the primary amplifier then is disconnected from a circuit node to which it is attached. The primary amplifier may then be taken out of its muting configuration. After, for example, configuring the primary amplifier as a comparator and calibrating its dc-offset voltage, the primary amplifier is placed back into a muting configuration. The secondary amplifier then is disconnected from the primary amplifier. The primary amplifier may subsequently be taken out of muting configuration to resume its normal function in the circuit.

Abstract: A voltage-to-frequency converter having an analog-to-digital converter, based on analog components, for converting samples of an analog signal into corresponding digital words and a digital-to-frequency converter, based on digital components, for converting the digital words into a train of pulses having a pulse repetition frequency related to the analog signal. With such an arrangement, the digital-to-frequency converter and the analog-to-digital converter are adapted to operate at different rates. Therefore, the analog-to-digital converter may be optimized at one operating rate while the digital-to-frequency converter is adapted to operate at a higher operating rate and over a wide range of operating rates. This arrangement thereby enables a slower, analog component based, analog-to-digital converter to be used fabricated with CMOS technology along with the higher, variable operating rate, digital component based, digital-to-frequency converter.

Abstract: Process for making an integrated-circuit (IC) chip with junction-isolated complementary bipolar transistors, and novel chip made by such process. P-type dopant is implanted and diffused in an N-type substrate to form a sub-collector for a pnp transistor and also is implanted and diffused in the substrate to form a P-well for the sub-collector of an npn transistor. N-type material is then implanted and diffused into the P-well to form the npn sub-collector, and also is implanted in the substrate to form part of an isolation wall for the pnp transistor. A P-type epitaxial (epi) layer is grown over the N-type substrate. N-type material is implanted and diffused in the epi layer to complete the isolation wall for the pnp transistor, and to form the collector for the npn transistor. P-type and N-type material is implanted and diffused in the P-type epi layer to form the bases and emitters for the npn and pnp transistors.

Abstract: A digitally controlled programmable attenuator maintains tight phase matching between attenuated signals over wide ranges of frequencies and power levels regardless of the selected attenuation level. This is achieved with a multi-tap ladder network that sets a desired tap-to-tap dB step-size, a plurality of unity gain digitally switched voltage-to-voltage buffers that are connected between the respective taps and a common output, and a fixed gain stage that sets the attenuator's overall gain/attenuation. The buffers maintain a high and substantially constant impedance whether turned on or turned off. Phase matching within 0.2.degree. at frequencies up to 300 MHz for 30 dB of gain variation has been realized.

Abstract: A variable gain amplifier includes an input transconductor having a transconductance that is variable in response to a first control signal, an output circuit having a transresistance that is variable in response to a second control signal and a gain controller responsive to a gain control signal x for providing the first and second control signals to the input transconductor and the output circuit. The amplifier has a voltage gain equal to the product of the transconductance and the transresistance. When the first control signal is a function (1+x) of the gain control signal and the second control signal is a function (1-x) of the gain control signal, the voltage gain of the amplifier is approximately an exponential function of the gain control signal.

Abstract: A method and apparatus for removing low frequency noise and any offsets common to a plurality of samples of a signal, for calibrating an offset level to be added to the signal to reference the signal to a desired reference level at an output of the apparatus, and for clamping an input voltage level to the apparatus to a desired voltage within an operating range of the apparatus. The apparatus includes a correlated double-sampling circuit which takes a first sample and a second sample of the analog signal, takes a difference between the first sample and the second sample to remove low frequency noise and any offsets common to both sample and which outputs a difference signal. In addition, the apparatus includes a black level correction circuit which adds an offset level to the difference signal to calibrate the offset level to be added to the difference signal so that the difference signal is at a desired reference level at an output of the apparatus.

Abstract: A residue amplifier includes input and output differential amplifiers. The output differential amplifier includes temperature-dependent current sources which compensate for temperature dependent gain variations within the input differential amplifier. Amplifier components are chosen to produce an overall gain equal to a ratio of fixed resistors, at a nominal temperature. The compensating current sources maintain this fixed gain value as the amplifier's operating temperature varies.

Abstract: A data transmission system including a telephone service subscriber loop utilized for transmission of data including telephone service signals; a splitter operable for splitting the subscriber loop into a first transmission path including a low pass filter which accommodates a continuation of telephone service signal transmissions along the subscriber loop and a second transmission path, said second transmission path including a capacitive element for attenuating the telephone service signals; and a digital subscriber loop transceiver coupled to the second transmission path for implementing high rate digital data transmission over the subscriber loop, the transceiver including a frontend processing circuit having a transmit path and a receive path, at least said receive path comprising a high pass filter for further attenuating said telephone service signals.

Abstract: An electrical overstress (EOS) protection circuit for protecting an active circuit of an integrated circuit including first and second clamping circuits series connected between a first input and a first input/output of the EOS protection circuit and third and fourth clamping circuits connected between a first output of the protection circuit and a second input/output. In embodiments of the present invention an EOS protection circuit provides protection for an active circuit while enabling a voltage at an input pad to the active circuit to exceed a power supply reference by more than several volts and to be less than a ground reference by more than several volts.

Abstract: In a circuit for use with a micromachined device having a movable mass that forms an inner electrode of a differential capacitor, oppositely phased square waves are applied to two outer electrodes of the differential capacitor. A reset voltage is applied to the inner electrode synchronously with the square waves to stabilize and control the potential on the inner electrode. The signal on the inner electrode is demodulated by sampling during a first half of the square wave and a second half of the square wave between applications of the reset pulse to obtain a voltage that does not contain noise due to the reset switch.

Abstract: An apparatus and method for protecting semiconductor switching devices from damage due to electrostatic discharge is provided. The apparatus detects the occurrence of an ESD event, and turns the switching circuit to an operating state in which electrostatic charge is dissipated through the switching circuit. In embodiments of the invention, the switching circuit is a CMOS inverter circuit and the apparatus includes a PMOS transistor that upon occurrence of an ESD event couples an output of the inverter circuit to ground to discharge the electrostatic charge.

Abstract: A method, and apparatus, for calibrating a delta sigma modulator. The delta sigma modulator includes an integrating amplifier circuit with an integrating capacitor for producing an output indicative of an amount of charge held on the integration capacitor. During the calibration mode, a feedback signal sampling section samples a feedback signal and transfers packets of charge corresponding to such sampled feedback signal to the integrating capacitor in each modulator cycle and an input signal section samples a calibration signal and transfers packets of charge corresponding to a portion of the calibration signal to the integrating capacitor in each modulator cycle. With such an arrangement, some charge is transferred to the integration capacitor in each modulator cycle thus reducing idle-tones.