Abstract: A switched-capacitor circuit that includes a first signal path disposed between a first input node and a first output node, and a second signal path disposed between a second input node and a second output node. The first and second switches can be alternately disposed within the first and second signal paths. An amplifier responsive to the switches can be provided, and its offset can be cancelled. The outputs of the amplifiers can be maintained, and this can involve buffering.

Abstract: A method and apparatus for removing low frequency noise and any offsets common to a plurality of samples of a signal, for calibrating an offset level to be added to the signal to reference the signal to a desired reference level at an output of the apparatus, and for clamping an input voltage level to the apparatus to a desired voltage within an operating range of the apparatus. The apparatus includes a correlated double-sampling circuit which takes a first sample and a second sample of the analog signal, takes a difference between the first sample and the second sample to remove low frequency noise and any offsets common to both samples and which outputs a difference signal. In addition, the apparatus includes a black level correction circuit which adds an offset level to the difference signal to calibrate the offset level to be added to the difference signal so that the difference signal is at a desired reference level at an output of the apparatus.

Abstract: A semiconductor die is packaged in a hermetically sealed ceramic dual in-line package (cerdip) with a non-standard polysulfone film, or with a paste made from the film, as a die attach material. A cerdip process heats to temperatures of at least about 380.degree. C. The paste is produced by dissolving the film with NMP or with a blend including NMP, and adding a thixotropic agent. The paste or film forms a bond in a cerdip with less than 5000 ppm moisture without using a getter.

Abstract: A digital filtering method that includes sampling an input signal at a first rate, integrating the signal, sampling the integrated version at a different rate, and combining the sampled integrated version with the input signal. The method can include again integrating the integrated version, sampling the twice integrated version at a third rate different from the first and second rates, and combining the twice integrated version with the integrated version and the input signal. The integrated version can be again integrated, the twice integrated version can be sampled at a third rate different from the first and second rates, and the twice integrated version can be combined with the integrated version. A common circuit component can be multiplexed to participate in two integrating steps.

Abstract: An apparatus and a method for providing ESD protection in integrated circuits is provided. The apparatus includes ESD protection circuits between interface pins and a substrate of the integrated circuit to discharge ESD current at one interface pin of the integrated circuit through the substrate to an ESD reference point at another interface pin. The ESD protection circuits include reverse breakdown devices that become conductive when a reverse breakdown threshold level is exceeded. The method includes discharging electrostatic charge from a first interface pin of the integrated circuit to a second interface pin through a substrate of the integrated circuit.

Abstract: A computed tomography imaging method includes receiving an analog beam intensity signal from a computed tomography scanner and converting the signal into a series of digital representations of the signal at successive points in time using a predetermined sample rate. Indications that a portion of the scanner has reached a certain position relative to the beam are received asynchronously with respect to the sample rate. The value of at least one of the digital representations is adjusted in response to the indications to obtain a corrected digital representation of the analog signal.

Abstract: A voltage divider and inverter provide a power-on-reset signal. The divider is placed between high and low power voltages, the divided voltage is the input to the inverter and the output of the inverter is the power-on-reset signal. The divider and inverter may be implemented on a single integrated circuit and accompany other, control and operational, circuitry on the integrated circuit. The divider is chosen so that the input to the inverter reaches the inverter's threshold voltage when the power voltage reaches a predetermined value.

Abstract: A bipolar transistor current mirror circuit has the bases of its input and output transistors connected together, but decouples the input transistor's collector from its base so that the mirror input voltage is no longer tied to the input transistor's base-emitter voltage. Instead, a separate base current source supplies sufficient base current to the mirror's input transistor to keep it in saturation, while a parasitic transistor that results from a junction isolated fabrication process drains off excess current from the base current source to keep it in balance with the mirror transistor base currents. The resulting input voltage is a function of the input transistor's saturated collector-emitter voltage, which is substantially lower than the base-emitter voltage and provides more voltage head room.

Abstract: A digital signal processor includes a control circuit for controlling transfer of instructions to and between a computation unit, a memory and an instruction cache. The memory includes a plurality of memory blocks. The control circuit includes a circuit for detecting a memory conflict condition when an instruction address on a first bus and a data address on a second bus both reference locations in one of the memory blocks in a single clock cycle. In response to the memory conflict condition, the instruction corresponding to the instruction address is fetched from the instruction cache when the instruction is stored in the instruction cache. When the instruction is not stored in the instruction cache, the instruction is fetched from memory and is loaded into the instruction cache. An internal memory conflict occurs when the instruction address and the data address reference locations in the same block of internal memory in the same clock cycle.

Abstract: A quadrature oscillator includes an amplitude control circuit that is based upon the trigonometric identity sin.sup.2 .omega.t+cos.sup.2 .omega.t=1. The amplitude control circuit, referred to as a Pythagorator, includes two squaring circuits. Each squaring circuit receives a respective quadrature oscillator signal and squares it. The outputs of the two squaring circuits are joined together so as to sum the outputs of the two squaring circuits to produce a sum of squares signal. This signal, a current in the preferred embodiment, is provided to damping diodes coupled to the outputs of the quadrature oscillator. The damping diodes produce a shunt positive resistance at the outputs of the quadrature oscillator in response to this current that has the effect of cancelling the shunt negative resistance of the regenerative elements of the oscillator thereby establishing the amplitude of the quadrature oscillator signals at a desired amplitude.

Abstract: A three state logic input recognizes three logic levels: an intermediate level in addition to the conventional "high" and "low" levels employed by binary logic systems. The three state device may be used in purely ternary logic systems or in "hybrid" systems which combine binary and ternary logic. In a preferred embodiment, the new three state logic device comprises a "passive driver" which is connected to produce one of three predetermined logic levels in corresponding to impedance paths from its input terminal through an external circuit to a positive or negative voltage supply. In hybrid ternary/binary applications, the new three state input device includes a decoder that is connected to decode the three predetermined logic levels provided by the passive driver into binary logic for use by associated binary logic devices. In a digital to analog converter application, the three state input device is employed to recognize both a binary logic and a control signal at one input pin to the DAC.

Abstract: A probe card tester for detecting defects occurring as a result of integrated circuit processing of a substrate having a plurality of space to conductors with a contact at each end of each conductor, includes: a probe card tester including a set of parallel resistors for connecting at least one in parallel with each conductor and a set of series resistors for connecting together the ends of the conductors to form a series resistance and a number of probe elements, one corresponding to each end of each conductor, for interconnecting the parallel and series resistors with the conductors for detecting defects bridging the conductors.

Abstract: A new differential ladder/comparator circuit reduces settling time delays in parallel analog to digital converters. A parallel analog-to-digital converter (ADC) includes a pair of differential resistor ladders having their taps connected to a group of comparators. The comparators produce digital "thermometer" scale outputs corresponding to analog signals impressed upon the differential ladders. By employing double-value resistors to form the "rungs" of the ladders and by connecting the comparators to the ladder taps in a way that increases the number of comparator inputs connected to the ladders' lower-order taps and decreases the number of comparator inputs connected to the ladders' higher order taps, the input impedance presented by the ladder/comparator combination is reduced in comparison with conventional differential ladder parallel ADCs.

Abstract: An integrated-circuit (IC) chip formed with a D-to-A converter (DAC) and an amplifier to receive the DAC output and to produce a corresponding signal for an output terminal. The chip includes control circuitry to prevent harmful instability in the signal at the output terminal during times that one or more power supply voltages are changing. The control circuitry includes a voltage-monitoring device which produces a RESET signal when a monitored supply voltage is beyond its nominal operating range. The RESET signal de-activates the amplifier input and output circuits, and following a short time delay after the start of RESET, disables the amplifier by killing the amplifier bias currents. The chip is arranged to receive a RESET signal from external devices, and to produce a RESET signal for any other devices in the system.

Abstract: A drive circuit and method for shaping the pair of complementary digital signals that drive a conventional CMOS switch are presented. The method adjusts the digital signals' duty cycles to set their cross point voltage levels so that at the cross points the voltage level at the CMOS switch's reference node is undisturbed with respect to its fully switched level. The drive circuit includes two pair of diode connected PMOS load transistors and NMOS load transistors that are connected at a pair of output terminals and a pair of switches. In one state, the NMOS load transistor is turned on while the switch cuts off its signal current so that the shaped digital signal's voltage at the output terminal is reduced to a precision limited low voltage. In the other state, the NMOS load transistor is turned off while the switch directs the signal current through the PMOS load transistor so that the shaped digital signal's voltage at the output terminal is increased to the PMOS load transistor's gate-to-source voltage.

Abstract: A Digital-to-Analog (D/A) converter with programmable transfer function includes a Main Converter and at least one Sub-Converter. Errors in the Main Converter are compensated for by programming the one or more Sub-Converters with compensation values determined during a Calibration Sequence. The Calibration Sequence measures the deviations of the transfer function of the Main Converter from the ideal at predetermined bit transitions of the digital input signal and generates representative separate digital signals for the one or more Sub-Converters. By combining these separate signals with the digital input signal, the net errors of the D/A Converter transfer function are reduced.

Abstract: The yield of good die from wafers is optimized by positioning the first level mask with respect to the wafer in accordance with a calculated alignment relationship based on physical characteristics of the wafer and the size of the die to be formed in the wafer. The calculated alignment relationship establishes the offset between the wafer and the mask which will result in the maximum available die. This offset is calculated by a computer which examines a number of prospective offsets between the center of one of the die and the center of the wafer. The number of available die is calculated for each such offset, and the offset which maximizes the available die from the wafer is determined.

Abstract: A micromachined device is packaged to reduce stiction. In one embodiment, a level of moisture is introduced in the package to create a very thin film over surfaces of the device. The device can also be packaged with a vapor deposition of an organic material after a wafer of devices has been separated into individual dies and the individual dies are placed in open containers. In another embodiment, a micromachined device is positioned in an open package and a liquid or solid organic material is disposed within the package so that when the device is sealed, the organic material vaporizes and coats portions of the die to reduce stiction.

Abstract: A clock oscillator having a pair of pins adapted for coupling to an external crystal, a first one of such pair of pins being adapted for coupling to an external clock. A switch, formed on the chip, is provided for electrically decoupling the crystal excitation circuit from one of the pair of pins in response to a control signal. In accordance with one embodiment of the invention, the switch is disposed between the output of a crystal excitation circuit and the second one of the pair of output pins and, in another embodiment, the switch is placed in circuit between the input to the crystal excitation circuit and the first one of the pair of pins. In each of these embodiments, when the switch is in a first condition, clock pulses are prevented from being coupled to the second one of the output pins, either: by preventing the external clock from feeding the input to the crystal excitation circuit; or, by preventing the output of the crystal excitation circuit from feeding the second one of the pair of pins.

Abstract: A differential switch accepts a binary control signal and its complement (which may be skewed with respect to the control signal) and latches both signals simultaneously. The latched output signals drive the control terminals of a differential switch pair which connects one of two terminals to a third terminal, depending upon the state of the control terminals. The differential switch may optionally include an inverter which complements the binary control signal, thus eliminating the need for external inversion of the control signal. The switch is particularly applicable for use in a digital to analog converter.