Abstract: A method for forming sub-micron sized bumps on the bottom surface of a suspended microstructure or the top surface of the underlying layer in order to reduce contact area and sticking between the two layers without the need for sub-micron standard photolithography capabilities and the thus-formed microstructure. The process involves the deposition of latex spheres on the sacrificial layer which will later temporarily support the microstructure, shrinking the spheres, depositing aluminum over the spheres, dissolving the spheres to leave openings in the metal layer, etching the sacrificial layer through the openings, removing the remaining metal and depositing the microstructure material over the now textured top surface of the sacrificial layer.

Abstract: A low dropout linear regulator utilizing a vertical PNP transistor as its pass element, integrated with CMOS circuitry. The vertical PNP transistor includes a P-well formed in a lightly doped N type substrate for its collector. An N-type region formed in the P-well is its base and a P-type region formed in the N-type region is its emitter. The emitter receives a variable input supply and the collector provides a regulated output signal to the load being driven. As the input voltage diminishes to less than a diode drop above the output voltage, the vertical PNP transistor tries to saturate and its associated parasitic NPN transistor turns on. To limit the effects of the parasitic NPN transistor and maintain a regulated output, a current limiter is connected between the input and the collector of the NPN parasitic transistor.

Abstract: A hysteresis circuit including first and second voltage reference circuits responsive to an input control signal for providing first and second voltage levels connected in series to produce a higher voltage level; a first switching circuit, responsive to the voltage reference circuits to turn on and provide an output drive signal when the higher voltage is reached; a second switching circuit, responsive to the first switching circuit turning on, for removing one of the first and second voltage levels to produce a lower voltage level; the first switching circuit turning off in response to the input level control signal decreasing below the lower voltage level.

Abstract: An analog to digital conversion system wherein a first chopper is responsive to a chop signal having a period T for passing an analog signal to an output with non-reversed polarity during a first portion of the period T and with reversed polarity during a second portion of the period T. An analog to digital converter produces a first set of at least one digital word corresponding to the analog signal with non-reversed polarity and an offset voltage and produces a second set of at least one digital word corresponding to the analog signal with reversed polarity and the offset voltage. A second chopper is responsive to the chop signal for passing to an output of the second chopper one of the produced first and second sets with non-reversed polarity, and passing to the output of the second chopper the other one of produced first and second sets with reversed polarity.

Abstract: A battery charger controller monitors the voltage across an associated battery charger's power element and opens a switch which inhibits current flow through the controller whenever the voltage across the pass element is substantially equal to zero.

Abstract: A gain compensating differential reference circuit that is used to match the gain of an input differential amplifier, and track and hold circuit at the input of an analog-to-digital converter. The gain compensating differential reference circuit includes a single-to-differential converter to convert a V.sub.REF signal into a V.sub.REF+ and a V.sub.REF- signals whose difference equals the full-scale range of the differential analog input to the A/D converter, a gain matching differential amplifier to process to the differential output of the single-to-differential converter, and a gain matching track and hold circuit to process the output of the differential amplifier. The output of the gain matching track and hold circuit has the same gain and full-scale range as the analog signals processed by the input circuitry of the A/D converter along the analog path.

Abstract: A guard ring with the same conductivity as a device pocket surrounds the pocket and a pocket isolation ring to establish a parasitic transistor that conducts current between the guard ring and the pocket when the pocket voltage is driven sufficiently below the substrate voltage. The guard ring is connected to a voltage supply for the circuit which, together with its shorter current path, allows the parasitic transistor to harmlessly divert current away from unwanted inter-pocket parasitic transistors.

Abstract: A data receiving and processing channel including analog signal processing circuitry operable for receiving data in the form of an input analog signal, and modifying the input signal in accordance with selected parameters so as to generate a modified analog input signal. According to one embodiment, there is provided a charge domain signal equalizer which initially transforms the modified analog input signal into a corresponding analog charge domain signal, the equalizer performing waveform shaping of the analog charge domain signal in accordance with a predetermined signal response template; a charge domain analog-to-digital converter operable for converting the analog charge domain signal into a corresponding digital signal; and a digital signal processor operable for recovering a digital bit stream from the digital signal which is indicative of the original data.

Abstract: An interlevel conductor defect characterization integrated circuit test structure including first and second spaced test pads, a conductor layer, an insulator layer between the conductor layer and the test pads; and a first interlevel conductor having a unit cross-sectional conductive area extending between the first test pad and the conductor layer, and a second interlevel conductor extending between said second test pad and said conductor layer and having a cross-sectional conductive area substantially greater than the unit area for detecting defects which restrict the current carrying capacity of said unit area of the first interlevel conductor but not the second interlevel conductor.

Abstract: A digital to analog converter (DAC) includes "shut-down" circuitry that opens connections between the DAC's reference and output sections. The shutdown circuitry provides reduced power consumption while permitting the DAC's control registers to retain their values. The invention is applicable to both stand-alone DAC and analog to digital converters (ADCs) which incorporate a DAC and can be microprocessor controlled.

Abstract: Using a power-up delay circuit on an analog/digital converter integrated circuit (i.e., an analog-to-digital converter or a digital-to-analog converter) to generate a signal delayed from power-up, and initiating a calibration of the converter upon detecting the delayed signal. In preferred embodiments, calibration can also be initiated in response to a signal on a calibration input pin of the integrated circuit, and the duration of the delay can be derived from a reference (e.g., by charging an external capacitor with it) or from the duration of a calibration operation. Circuitry can be provided to automatically place the circuit in an operating mode upon power-up that keeps the integrated circuit in shutdown mode when it is not converting or calibrating.

Abstract: An asynchronous digital sample rate converter includes a random access memory for storing input data values and a read only memory for storing a reduced set of interpolation filter coefficients. Input data is written to the random access memory at the input sample rate. Output samples are provided from a multiply/accumulate engine which given a stream of input data and filter coefficients produces an output sample upon request at the output frequency. The initial address for reading input data from the random access memory, and the addresses for coefficients from the read only memory are provided by an auto-centering scheme which is a first order closed loop system with a digital integrator fed by an approximation of the input to output sample rate ratio. This auto-centering scheme may include a feed forward low pass filter to cancel steady state error, and an interpolated write address to reduce noise.

Abstract: An alarm based upon the voltage across a linear regulator's pass transistor and the regulator's load current alerts operational circuitry which obtains power through the regulator when the voltage across the pass transistor may be insufficient for proper voltage regulation. The alarm's trigger voltage is adjusted in response to variations in the regulator's output current.

Abstract: A method for making micromachined structures that includes pinpoint polysilicon bumps for eliminating the stiction problem associated with elements of the micromachined structure, such as movable or fixed beams. The pinpoint polysilicon bumps provide a reduced contact area for the beam which reduces the chances that there will be a stiction problem due to static or surface charge. The method takes advantage of an edge alignment technique to achieve a geometry for pinpoint bump structures of as low as 0.20 .mu.m. The bump structures are located in a region of the movable and fixed beams at the edge adjacent the gaps between the interleaved fingers. The method forms bump structures that have a circular design. The formation of the bump structures is carefully controlled with respect to the overlap of these bump structures into interdigitated structures.

Abstract: A protection circuit inhibits saturation and damage of sensitive circuit elements when an input signal goes out of a nominal input range. The protection circuit includes an out-of-range detector which compares the input signal to reference levels to determine if it is within the range. If it is not, a control circuit substitutes a supplemental signal that is slightly out of range, but not so far out of range as to cause any substantial saturation. Supplemental signal sources that produce supplemental signals slightly outside the high and low ends of the range with error margins, not more than about 750 mV, that lie just outside the range; an out-of-range input is replaced by the supplemental signal with the closest value. The invention is particularly applicable to multistep/subranging analog-to-digital/converters.

Abstract: A micromachined device has first, second, and third electrodes forming a differential capacitor, and first and second drivers for providing clocked signals to the first and second electrodes. The drivers each have supply leads coupled to first and second reference voltage supplies via fixed first and second resistors, and also coupled together with variable resistors for trimming an offset so that electrostatic forces are balanced.

Abstract: According to embodiments of the present invention, a driver circuit, has first and second reference voltage rails for receiving first and second reference voltages, has first and second inputs for receiving an input differential signal and has first and second outputs for providing an output differential signal. The driver circuit comprises a first CMOS transistor, a second CMOS transistor, and first, second and third current sources. Positive voltage levels with respect to ground at the first and second outputs, are within typical acceptable ECL output voltage levels.

Abstract: A comparator combines unbalanced differential input amplifiers to produce a balanced input stage that forces the comparator output to a predetermined state whenever the first differential amplifier enters dropout. The comparator's second differential amplifier is imbalanced to overcome the variable offset voltage which creates the comparator's hysteresis voltage. Its first differential amplifier is imbalanced to compensate for the imbalance of the second amplifier, thereby producing an input stage which is balanced overall and free of input offset voltages that would otherwise be present.

Abstract: A dynamic phase selector phase locked loop circuit includes: an A/D converter for receiving an input to be sampled; a phase detection circuit for determining the phase error between the input signal and a clock signal; a clock circuit, responsive to the phase detection circuit, for providing the clock signal to the A/D converter for timing the sampling of the input signal; the clock circuit including a delay circuit having a number of delay taps; and a phase selector circuit, responsive to the phase detection circuit, for initially gating the clock signals to the A/D converter from the clock circuit, and enabling one of the delay taps to dynamically adjust the phase of the clock signal and reduce the initial phase error.

Abstract: A MOS ROM architecture which is fast-switching, requires almost no current under static conditions and only small current while switching, does not require a precharge mechanism and exhibits high immunity to electrical noise. A flash converter using this ROM architecture has a "one of" circuit driving a ROM encoder stage. The ROM constitutes a "one-of" to Gray- or modified Gray code encoder, or a "one-of" to binary encoder. Each bit cell in the ROM has a single NMOS transistor with its drain connected to either zero volts (representing logical 0) or to a V.sub.DD supply of, for example, 5 volts (representing logical 1). The transistor's source is connected to the bit line. All bit cell transistor gates for a given ROM address (i.e., location) are driven in parallel by an enable/disable signal. Preferably, the N-channel transistors whose drains are connected to logical 0 are about twice as large as those whose drains are connected to logical 1, to achieve desirable drain-to-source "on" resistance, R.sub.