Abstract: A method and apparatus for providing a sub-ground plane for a micromachined device. The sub-ground plane is formed in or on the substrate. Above the sub-ground plane is a dielectric and then a discontinuous conductive layer used for interconnects for parts of the micromachined device. A movable microstructure is suspended above the interconnect layer. A conductive layer can be suspended above the movable microstructure. In one embodiment, the sub-ground plane is diffused into the substrate or a well in the substrate, and is of an opposite type from the type of silicon into which it is diffused. Alternatively, the sub-ground plane is formed from a conductive layer, deposited over the substrate before the layer used for interconnects.

Abstract: A method and apparatus for providing a conductive plane beneath a suspended microstructure. A conductive region is diffused into a substrate. A dielectric layer is added, covering the substrate, and then removed from a portion of the conductive region. A spacer layer is deposited over the dielectric and exposed conductive region. A polysilicon layer is deposited over the spacer layer, and formed into the shape of the suspended microstructure. After removal of the spacer layer, the suspended microstructure is left free to move above an exposed conductive plane. The conductive plane is driven to the same potential as the microstructure.

Abstract: A digitally controlled oscillator in a digital phase-locked loop provides an additional output signal which indicates the time difference between clock pulses output from the digitally controlled oscillator and clock pulses of an ideal clock signal of the same average frequency. This additional signal is called a residue signal. This residue signal may then be used to extrapolate or interpolate outputs of continuously variable interpolation or decimation filters using the output clock signal of the digital phase-locked loop generated according to the digitally controlled oscillator. Because the residue signal may be used in interpolation or decimation filters, it is also applicable to analog-to-digital converters, digital-to-analog converters and sample rate converters which use such filters. The digital phase-locked loop circuit is simpler than previous circuits because a conventional overflowing accumulator may be used, which is a first order system, rather than a higher order multi-bit noise shaper.

Abstract: An error compensated current mirror includes a current mirror circuit having an input transistor and an output transistor; a bias current source in series with the input transistor and a load current source in series with said output transistor; the load current source including a load current source transistor in series with a load current source impedance; an input terminal connected between the bias current source and the input transistor; a buffer circuit including a transistor having its base connected between the load current source and the output transistor; a buffer biasing current source connected in series with the buffer circuit, the buffer biasing current source including a buffer biasing current source transistor in series with a buffer biasing current source impedance; said buffer biasing current source transistor being a replica device of the output transistor; an output terminal connected between the buffer circuit and the buffer biasing current source; and a compensating circuit including a c

Abstract: A diode-connected transistor device for IC protection against electrostatic discharge (ESD) that functions as a transistor in the active region during an ESD event. The device cell includes an annular collector at the outer reaches of the cell, a circular base diffusion concentric with the collector, and an annular emitter near the outer edge of the base. The base and emitter regions are connected together by metallization external to the transistor cell. With the base contact enclosed by the annular emitter, during an ESD spike the initial reverse bias current flow is from the collector, under the emitter diffusion and out of the base contact. Eventually, as the magnitude of the ESD spike increases, the reverse biased current becomes sufficient to locally forward bias the base-emitter junction changing the primary ESD current path from collector to base, to collector to emitter, thus lowering the ESD current density in the active base-collector junction.

Abstract: A micromachined device has a plurality of rotationally dithered masses that are used to sense acceleration. To eliminate common modes, the masses are dithered in an equal and opposite manner. To help maintain this relationship between the movement of the masses, a coupling fork provides minimal resistance to anti-phase movement and substantial resistance to in-phase movement. Electrodes are used to detect changes in capacitance between the masses and the substrate resulting from rotation of the device about a radial axis of a mass. These electrodes are electrically connected to eliminate gradients that are caused by external forces and manufacturing differences. Four masses or more can be provided, arranged in a two-dimensional array, such as a square or hexagon with a coupling fork provided between each pair of masses, and with electrodes connected to eliminate gradients.

Abstract: A micromachined device has two suspended masses positioned near each other, each of the masses being dithered along a dither axis. Two couplings, each including an arcuate member and an anchored support beam, are provided between the masses to allow relative anti-phase movement and to resist relative in-phase movement. The coupling extends around a region intermediate the masses where a dither detection device is disposed.

Abstract: A control system for a permanent magnet synchronous motor includes a position estimator means having for cross correlating the back EMF of the unenergized winding with a reference waveform to determine the estimated position of the rotor for determining rotor angle position error; an error compensator, responsive to the rotor angle position error, for determining the angular speed of the field; an angle generator, responsive to the angular speed of the field, for generating the field angle position; and a waveform generator, responsive to the rotor angle position, for generating a periodic signal corresponding to each winding and designating a segment of that signal for driving that winding to adjust the field speed to the rotor speed.

Abstract: A monolithic digital signal processor includes a core processor for performing digital signal computations, an I/O processor for controlling external access to and from the digital signal processor through an external port, first and second memory banks for storing instructions and data for the digital signal computations, and first and second buses interconnecting the core processor, the I/O processor and the memory banks. The core processor and the I/O processor access the memory banks on the first bus without interference on different clock phases of a clock cycle. The internal memory and the I/O processor of the digital signal processor are assigned to a region of a global memory space, which facilitates multiprocessing configurations. In a multiprocessor system, each digital signal processor is assigned a processor ID. The digital signal processor includes a bus arbitration circuit for controlling access to an external bus through the external port.

Abstract: A Half-Gray digital encoding technique is disclosed for use in a parallel analog-to-digital converter (ADC) that reduces the ADC's output errors. A thermometer code, proportional to the ADC's analog input, is provided to a decoder which produces 2.sup.n output lines with one active line for each binary 0-to-1 transition in the thermometer code. A 1-of-(2.sup.n)-to-Half-Gray encoder converts the decoder output to a Half-gray code which has error reducing properties. The Half-Gray code is then provided to an n-bit Half-Gray-to-binary decoder for converting the Half-Gray code to a standard Binary code ADC output.

Abstract: A low drop-out voltage regulator is compensated by providing a compensation capacitor across an output terminal of the regulator and an output lead of an input stage which compares a reference voltage and a voltage derived from a regulated output signal at the output terminal. The output from the input stage is inverted without gain before being provided to an output stage. This inversion allows Miller compensation with the compensation capacitor.

Abstract: A signal conditioning circuit compresses an audio signal by producing a gain signal that is a function of the time-averaged audio signal and a compression ratio, and amplifying the audio signal by an exponential function of the gain signal. The conditioning circuit merges the functions of buffering the audio signal and producing a full-wave rectified version of the audio signal into a single buffer circuit. An averaging circuit generates a time-averaged signal in response to the full-wave rectified signal. An interface circuit includes downward expansion, compression and limiting circuits for scaling the time-averaged signal with a low compression ratio when it is less than a break point, with a selected compression ratio when it is between the break point and a rotation point, and with a high compression ratio when it exceeds the rotation point. The interface circuit produces the gain signal in response to the time-averaged signal and the corresponding compression ratio.

Abstract: Both differential and single-ended band-switchable VCOs are described. The single-ended version of the voltage controlled oscillator in its most basic form includes a load, two transistors, two delay elements, and a switchable current source. The first transistor includes a collector, an emitter and a base coupled to the load to form an output terminal for providing an oscillator output signal. The first delay element is connected between the collector and the base of the first transistor. The second transistor includes a collector, an emitter and a base connected to the base of the first transistor. The second delay element is connected between the collector of the first transistor and the collector of the second transistor.

Abstract: A circuit construction for biasing near a pocket containing a power supply potential circuit element in a junction-isolated circuit. In normal operation if the polarity of the supply voltage is reversed from that intended the pocket is disconnected. To achieve this, in one embodiment the emitter of a transistor is connected to the positve supply voltage. The collector of that transistor is used to bias the pocket, containing a circuit element, which in normal operation should receive the supply voltage. When the supply voltage is reversed, the emitter-base junction is reverse biased and the collector-base junction is turned off. The pocket is thus disconnected from the supply during supply reversal. The transistor may also have a second collector to handle reinjection of carriers when it is saturated. This second collector can be connected to the base or used by other circuits to detect when saturation occurs.

Abstract: A watchdog circuit accepts an output signal from a monitored circuit such as a microprocessor to determine whether the monitored circuit is operating appropriately or has incurred an error. The monitored circuit must periodically assert the output signal to prevent the watchdog circuit, which imposes both upper and lower frequency bounds on the assertion of this signal, from "timing out" and setting a watchdog error alarm. The watchdog circuit may be combined with other circuits, such as power on reset, battery back-up switching, etc., within a microprocessor supervisory circuit.

Abstract: A differential string DAC is provided including a coarse DAC which includes a plurality of coarse resistors connected in series between first and second reference voltage leads. A positive sub-DAC includes a plurality of positive sub-DAC cells, each positive sub-DAC cell including a multitude of series-connected fine resistors. A negative sub-DAC includes a plurality of negative sub-DAC cells, each negative sub-DAC cell including a multitude of series-connected fine resistors. Each coarse resistor is electrically connected in parallel with one positive sub-DAC cell and one negative sub-DAC cell. The positive sub-DAC cell and negative sub-DAC cell are substantially symmetrically disposed about the corresponding coarse resistor. Due to the differential arrangement and symmetrical layout of the DAC, INL errors due to process gradients in one direction across the DAC are greatly reduced. Process gradients in a second orthogonal direction are not of great concern as they cause much smaller INL errors.

Abstract: A method and apparatus for phase locking to an input signal and outputting a sigma-delta modulated control signal. The method and apparatus of the present invention provide a sigma-delta modulated control signal which can be utilized by any one of a decimator for decimating a digital data at a first data rate to a digital data at a second data rate and an interpolator for interpolating a digital data at a first data rate to a digital data at a second data rate. The decimator and the interpolator can be utilized in any one of an analog-to-digital converter, a digital-to-analog converter and a digital-to-digital converter. In one embodiment, a period of the input signal is determined and fed to a phase-locked loop which includes a sigma-delta modulator for providing the sigma-delta modulated control signal. The phase-locked loop also includes a phase detector for determining a phase and a frequency-difference between the input signal and a conversion signal generated by the phase-locked loop.

Abstract: A method and apparatus for analog-to-digital conversion using sigma-delta modulation of the temporal spacing between digital samples are provided. The method and apparatus include sigma-delta modulation of the time-base such that errors produced by non-uniform sampling are frequency-shaped to a high frequency region where they are reduced by conventional digital filtering techniques. In one embodiment, a sigma-delta ADC receives an analog input signal and converts the analog input signal to digital samples at an oversampling rate. A decimator, coupled to the sigma-delta ADC, receives the digital samples and decimates the digital samples to produce the digital samples at a preselected output sample rate, less than the oversampling rate. An ADC sample rate control circuit, coupled to the ADC, receives a frequency select signal representing the preselected output sample rate, and produces a noise-shaped clock signal for controlling operation of the ADC at the oversampling rate.

Abstract: The invention comprises a hardware constructed address generator for a circular buffer which can be of any size and be in any position in memory. The address generator calculates both an absolute value and a wrapped value and selects one in accordance with whether the wrapped value falls within the boundaries of the buffer.

Abstract: To calibrate an accelerometer having a ground plane, two fixed beams, and a movable beam centered between the fixed beams, a force/acceleration reference is produced by providing a change in voltage on the ground plane. Circuit gain is adjusted so that the output response indicates the force reference. The calibration method can be used to self-calibrate in response to an event, such as a power-up state. The calibration can be performed without shaking and can be used with either open or closed loop circuits.