Abstract: An ESD protective clamp device comprised of a two-terminal diode formed in an isolated chip cell. The lower part of this chip cell region contains a buried layer of silicon with P-type dopant, and the upper part is an epitaxial layer also with P-type dopant. An annular (ring-shaped) anode plug segment is formed at the outer reaches of the epitaxial layer with P+ doping. At the interior central region is an N-type plug circular in horizontal cross-section and concentric with the annular plug. This central plug serves as the cathode. Electrical connections are made to anode and cathode to provide interconnection with an IC circuit with a MOM capacitor to be protected.

Abstract: A device for producing an output voltage which is proportional to an applied magnetic field. The device includes a plurality charge injection regions, a corresponding plurality of charge exit regions, and a charge transfer region. The charge transfer region includes gate electrodes which serve to propagate at least one isolated charge packet across the charge transfer region in a predetermined direction from the charge input region to the charge output region. The charge packet is subject to the applied magnetic field which is perpendicular to the charge transfer region so as to induce a resultant potential that is orthogonal to both the applied magnetic field and the predetermined direction. Furthermore, the resultant potential effects a lateral redistribution of charge carriers in the packet. A recirculation configuration allows for a recycling of the packet from the output region back to the input region in order to accommodate a continuation of the redistribution of charge carriers.

Abstract: A charge pump system for charging an integrating capacitor includes a current source for supplying a first current of a first polarity, a second current of the opposite polarity which is a fraction of the first current, a third current of the opposite polarity, and a fourth current of the first polarity which is a fraction of the third current, and a switching device for simultaneously interconnecting both the first and second currents to the integrating capacitor to provide a first pump down charging current which is the fractional difference between the first and second currents, and also alternately selectively interconnecting both the third and fourth currents to the integrating capacitor to provide a second pump up charging current which is a fractional difference between the third and fourth currents and opposite in polarity to the first charging current.

Abstract: A MOS comparator which includes a capacitor connected in an electrical path between two amplification stages. The comparator also includes a voltage source, and a switch is provided between the voltage source and the input of the second stage. A variability of electrical parameter of the voltage source can be matched with a parameter of the amplification stage. The comparator can also include another switch between another voltage source and a third stage, with the two voltage sources providing different voltages. A comparator gain stage includes circuitry for deriving a differential current from the two voltages. Circuitry is also provided for loading the differential current to derive an amplified difference voltage. Further circuitry is provided for bypassing the loading circuity to reduce a quiescent voltage drop associated with the loading circuitry.

Abstract: A mixer section is combined with a post-mixer linearizer to counteract the nonlinear transconductance characteristics of the RF input section of the mixer thereby increasing the overall linear response of the mixer. The post-mixer linearizer has a response that is increasingly non-linear outside the non-linear operating range of the RF input section. This non-linear response compensates for the decreasingly non-linear response of the RF input section. Current mirrors in the post-mixer linearizer increase the rail-to-rail headroom of the mixer while maintaining high gain. An input driver is coupled to the mixer that provides quick switching transitions in the mixer to reduce noise effects. The mixer also includes a gain control circuit that provides linear-in-decibel gain control.

Abstract: A resistor programmable temperature switch for indicating that a preselected trip temperature has been reached includes first and second bipolar trasistors of like polarity having a fixed ratio of emitter areas; means for connecting the emitters of the first and second transistors to a common terminal; first and second current sources for providing first and second predetermined currents to the collector of the first and second transistors, respectively; a third transistor; means connecting its control terminal to the first current source and a first load terminal connected to the base of the first transistor for operating the first transistor to conduct the first predetermined current from the current source; means for interconnecting a second load terminal of the third transistor with a power supply terminal; a resistor network including first and second resistors connected between the base of the first transistor and the common terminal for biasing the base of the second transistor to a fraction of the bas

Abstract: A wide-band voltage controlled amplifier includes a differential stage and a gain control stage. The differential stage responds to a differential input signal by apportioning a bias current between the two sides of the differential stage. The gain control stage responds to a variable gain control voltage by further dividing the current in each side of the differential stage to set the gain of the VCA. The negative resistance circuit is connected across the differential stage to supply a correction current that reduces the non-linearity distortion in the current supplied to the gain control stage, which in turn improves the linearity of the VCA's output voltage.

Abstract: An explicit RMS detector sequentially performs the square, mean and square-root operations in the log domain. An input signal is first applied to a log converter, and then to a times two multiplier which squares the input signal. A log filter averages the log square input signal for a predetermined period to approximate the "mean" operation, after which a times one-half multiplier operates on the log mean-square input signal to compute the square root. An exponentiator exponentiates the resulting log root-mean-square input signal to produce an output signal that approximates the RMS value of the input signal for the predetermined period.

Abstract: A servo system for controlling the position of a read/write head in a disk drive is provided. The servo system includes an input terminal for sequentially receiving a plurality of input signal bursts of a burst pattern, wherein the input signal bursts include positional information of the head. Demodulation circuitry, coupled to the input terminal, sequentially demodulates each input signal burst and provides a demodulated signal for each burst. An ADC, coupled to the demodulation circuitry, sequentially converts each demodulated signal. The ADC converts a first demodulated signal corresponding to the first of the plurality of input signal bursts before the demodulation circuitry completes demodulating the next of the plurality of input signal bursts. In a preferred embodiment, the ADC converts a demodulated signal corresponding to a first input signal burst while the demodulation circuitry demodulates a signal corresponding to a second, and subsequent, input signal burst.

Abstract: A micromechanical sensing apparatus includes a micromechanical sensor having a stationary element and a movable element which are electrically conductive, and a sensing circuit responsive to the micromechanical sensor for generating an output indicative of a sensed quantity. The sensing circuit may have a closed loop configuration or an open loop configuration. The sensing apparatus further includes an actuation circuit for applying to the micromechanical sensor an actuation signal, such as a test signal, for electrostatically deflecting the movable element relative to stationary element. The actuation circuit includes circuitry for limiting the bandwidth of the actuation signal such that the deflection of the movable element does not exceed maximum deflection limits. In the closed loop configuration, the bandwidth of the actuation signal is preferably limited to less than or equal to the closed loop bandwidth of the sensing circuit.

Abstract: A polysilicon ground plane is formed over dielectric layers and under a suspended, movable mass in a surface micromachined device. The process includes steps of forming a diffused region in a substrate, forming the dielectric layers over the substrate, forming the ground plane over dielectric layers, and forming a body having a suspended mass, a first anchor extending from the mass down to the diffused region, and a second anchor extending from the mass down to the ground plane. The two anchors are formed simultaneously. The ground plane, which can be formed with only three additional steps over prior processes, serves as a ground plane to control changes and also as a local interconnect.

Abstract: A method and apparatus for phase locking to an input signal and outputting a sigma-delta modulated control signal. The method and apparatus of the present invention provide a sigma-delta modulated control signal which can be utilized by any one of a decimator for decimating a digital data at a first data rate to a digital data at a second data rate and an interpolator for interpolating a digital data at a first data rate to a digital data at a second data rate. The decimator and the interpolator can be utilized in any one of an analog-to-digital converter, a digital-to-analog converter and a digital-to-digital converter. In one embodiment, a period of the input signal is determined and fed to a phase-locked loop which includes a sigma-delta modulator for providing the sigma-delta modulated control signal. The phase-locked loop also includes a phase detector for determining a phase and a frequency-difference between the input signal and a conversion signal generated by the phase-locked loop.

Abstract: An asymmetrical ramp generator system for a pulse width modulator includes a complementary clock circuit; a first symmetrical dual ramp generator, responsive to the clock circuit, for generating first and second ramps having a predetermined voltage range and extending for a period equal to or greater than one half the clock cycle; a comparator device, responsive to the first and second symmetrical ramps and to a reference level within the predetermined voltage range of the first and second ramps, for generating corresponding dual first and second asymmetrical drive signals; and a second asymmetrical dual ramp generator, responsive to the first and second asymmetrical drive signals, for generating third and fourth asymmetrical overlapping ramps which extend beyond the predetermined voltage range.

Abstract: A CMOS amplifier input stage including an NMOS differential pair connected in parallel with a PMOS differential pair. Each pair is connected to a tail-current transistor of the same type, and the combined circuits are coupled between positive and negative supply rails. The gates of the tail-current transistors receive the amplifier input signal to provide adaptive biasing of the differential pairs, resulting in a total combined transconductance for both differential pairs which is at least approximately constant with changes in input signal level, thereby enlarging the available common-mode input signal range of the amplifier.

Abstract: A gain control circuit provides linear-in-decibel gain control for an RF signal variable gain amplifier. The gain control circuit utilizes the transconductance characteristics of bipolar transistors to generate a logarithmic relationship between a gain control current and an amplifier bias current. The gain control circuit comprises essentially a current mirror having two transistors with a resistor coupled between the associated base terminals of the two transistors. A third transistor and a resistor are also provided to absorb the gain control current. The gain control current is applied to the base of a first one of the two transistors and a voltage is thereby established across the resistor. This voltage subtracts from the base-to-emitter voltage of the second transistor thereby producing a corresponding exponential reduction in the current through the second transistor. This current is provided to a gm stage, whose gain is linearly proportional to this current.

Abstract: An SOI/DI IC chip including a handle wafer in the form of a section of silicon substrate contiguous with the layer of insulation beneath the silicon slice containing the device regions separated by trenches filled with low-conductivity polysilicon dielectric. One of the trenches is etched through the layer of insulation, and the polysilicon in that trench is doped to provide desired electrical conductivity to establish electrical contact with the handle wafer. Metallization is applied over the top of this one trench to make possible electrical connection to the handle wafer from above the chip by use of conventional wiring techniques.

Abstract: An integrated-circuit (IC) chip formed with a D/A converter (DAC) having a digitally-programmable circuit for setting the full-scale output range of the DAC by controlling its gain. The IC chip further includes analog sync level generator circuitry for driving computer graphics CRTs. The sync level generator circuitry is integrated with the DAC circuitry in such a way that the sync signal levels track changes made to the full-scale operating output range of the DAC and also track with changes in operating conditions such as varying temperature, supply voltage and RSET resistance in the DAC current control circuitry.

Abstract: A logarithmic amplifier gain stage for supplying, in response to an instantaneous input signal, an output signal corresponding to a logarithmic value of the input signal. The gain stage includes a transistor amplifier having an input that receives the input signal and an intermediate output that supplies an intermediate output signal. A full-wave detector having an input coupled to the intermediate output of the transistor amplifier receives the intermediate output signal and supplies the output signal wherein the detector includes a rectifier comprising transistors having different effective emitter areas.

Abstract: A current source DAC is provided including a plurality of current source cells arranged in an array of a plurality of columns and rows. Among the plurality of current source cells is a plurality of least significant bit cells, wherein each least significant bit cell includes at least one current source cell. The plurality of least significant bit cells includes current source cells from among a centrally located column of the array. Also among the plurality of current source cells is a plurality of most significant bit cells. Each most significant bit cell includes a plurality of current source cells electrically added together and physically located along a diagonal path across the columns and rows of the array. The current source cell include CMOS transistors. The physical layout and electrical connection scheme reduces DNL errors due to transistor process gradients.

Abstract: A sense amplifier for determining the state of a memory cell of a random access memory includes first and second transistors connected in a differential amplifier configuration. The first and second transistors have control electrodes coupled to Bit and Bit B lines, respectively, for sensing a state of the memory cell. The sense amplifier further includes third and fourth transistors connected in a differential amplifier configuration. The differential amplifier configuration has an offset error and provides differential outputs for indicating the state of the memory cell during a read phase. The sense amplifier further includes first and second capacitors respectively coupled between the control electrodes of the third and fourth transistors and a reference potential, and a feedback circuit for coupling voltages representative of the offset error to the first and second capacitors during a nulling phase in which the Bit and Bit B lines are not being read.