Abstract: A micromachined force sensor containing separate sensing and actuator structures. A member is suspended above the substrate so that it is movable along an axis in response to a force. The member includes a set of parallel sense fingers and a separate set of parallel force fingers. The sense fingers are positioned between fingers of two sense plates, to form a first differential capacitor, whose capacitance changes when the member moves in response to a force along the axis. The change in capacitance induces a sense signal on the member, which permits the measurement of the magnitude and duration of the force. The force fingers are positioned between fingers of two actuator plates, to form a second differential capacitor. The sense signal can be used to provide feedback to the second differential capacitor to generate different electrostatic forces between the force fingers and the two actuator plates, to offset the force applied along the preferred axis.

Abstract: A switched capacitor (SC) network is used in conjunction with a single PN junction to form a switching bandgap reference voltage circuit. The circuit includes an amplifier having an inverting input, a noninverting input, and an output; a first capacitor having a first capacitance (C.sub.1) coupled between the amplifier inverting input and a first common voltage source; a second capacitor having a second capacitance (C.sub.2) coupled between the amplifier inverting input and the amplifier output; a transistor having a base, a collector, and an emitter, the base and collector being coupled to the first common voltage source, and the emitter being coupled to the amplifier noninverting input. Two current sources are coupled to the transistor to bias the transistor to a one level during a precharge mode and a second, higher level during a reference voltage mode. A switch is connected in parallel with the second capacitor.

Abstract: A switched-capacitor DAC system includes an integrator circuit including an op amp having an input lead, an output lead and an integrator capacitor connected between the input lead and the output lead. A sampling switch is operable to connect an input capacitor to be charged by an input voltage during at least one of first and second non-overlapping time intervals, wherein the first time interval is subdivided into first and second non-overlapping sub-intervals and the second time interval is subdivided into third and fourth non-overlapping sub-intervals. A transferring switch is operable to connect the input capacitor to transfer charge from the input capacitor to transfer charge from the input capacitor to the integrator capacitor during at least one of the first and third sub-intervals. A discharging switch is operable to connect the input capacitor to a discharge node during at least one of the second and fourth sub-intervals.

Abstract: An analog-to-digital converter employs a sigma-delta modulator that produces a pulsed output with an average duty cycle that varies with an analog input to the modulator. A counter averages the modulator's output duty cycle, and feeds the averaged information onto a one-line transmission circuit for delivery to a remote location. Both the sigma-delta modulator and the counter are synchronized to the same local clock, so that the counter's duty cycle remains substantially constant even if the clock frequency varies. This allows for a simple clock configuration that can be integrated along with the sigma-delta modulator and counter on a single IC chip of reasonable size. When used for temperature sensing, the counter's output duty cycle provides an indication of the locally sensed temperature, independent of temperature-induced variations in the clock frequency.

Abstract: An improved magnitude amplifier (magamp) is provided for a serial-type A/D converter. The magamp includes an improved differential input amplifier circuit to which offset circuitry is connected. These elements may be implemented in a single integrated circuit chip or as separate discrete circuits in hardware. The differential input amplifier circuit includes two pairs of differential input transistors, a comparator, and current switching control transistors. The comparator provides outputs that drive the current switching control transistors. The current switching control transistors are connected below the input transistors and not above the input transistors to reduce the parasitic capacitive loading at the outputs of the differential input amplifier circuit and increase the speed of the magamp. The offset circuitry provides the appropriate signals for aligning the output signals for output to the next stage magamp.

Abstract: A method and apparatus for phase locking to an input signal and outputting a sigma-delta modulated control signal. The method and apparatus of the present invention provide a sigma-delta modulated control signal which can be utilized by any one of a decimator for decimating a digital data at a first data to a digital data at a second data rate and an interpolator for interpolating a digital data at a first data rate to a digital data at a second data rate. The decimator and the interpolater can be utilized in any one of an analog-to-digital converter, a digital-to analog converter and a digital-to digital converter. In one embodiment, a period of the input signal is determined and fed to a phase-locked loop which includes a sigma-delta modulator for providing the sigma-delta modulated control signal. The phase-locked loop also includes a phase detector for determining a phase and a frequency-difference between the input signal and a conversion signal generated by the phase-locked loop.

Abstract: Charge pump structures (100, 110) are disclosed having a reservoir capacitor (40, 86) and a pump capacitor (26, 84) embedded in a switch network. Each of the switches (120) in the network is formed as an MOS transistor having a gate (122) which defines an array of spaced apertures (124) and a plurality of sources (130) and drains (132) each disposed beneath a different one of the apertures.

Abstract: A differential amplifier operating as a magnitude amplifier may be used in a serial-type A/D converter. The differential amplifier uses complementary differential emitter pairs for folding and aligning a differential input signal. The differential input signal has a first signal and a second signal each of which is fed to one of two input circuits. One input circuit includes a bipolar npn transistor and a current sink and the other includes a bipolar pnp transistor and a current source. The outputs of the input npn transistors feed a differential pair of output pnp transistors. The emitters of the output pnp transistors are coupled, with the signal on the emitters following the lower of the differential input signals. The outputs of the input pnp transistors feed a differential pair of output npn transistors. The emitters of the output npn transistors also are coupled, with the signal on the emitters following the inputs in a predetermined manner.

Abstract: An integrated circuit including a semiconductor substrate, a semiconductor layer formed on the substrate, a desired bipolar transistor formed in the semiconductor layer. First and second parasitic elements are formed in the integrated circuit. An element is provided which detects when the second parasitic element becomes active or which prevents increase of the collector-to-emitter voltage of the desired bipolar transistor in response to current flowing through the second parasitic transistor. This element may be a semiconductor region formed in the semiconductor layer. The transistor may be an npn or pnp type transistor manufactured according to a complementary bipolar process or other process which results in a transistor with first and second parasitic elements. The present invention is also well-suited for use in the output stage of an operational amplifier.

Abstract: A method for providing a conductive ground plane beneath a suspended microstructure. A conductive region is diffused into a substrate. Two dielectric layers are added: first a thermal silicon dioxide layer and then a silicon nitride layer. A first mask is used to etch a ring partially through the silicon nitride layer. Then, a second mask is used to etch a hole through both dielectric layers in a region having a perimeter that extends between the inner and outer edges of the ring. This leaves the conductive region exposed in an area surrounded by a ring that has the silicon dioxide layer and a narrow silicon nitride layer. The ring is surrounded by an area in which the silicon dioxide and silicon nitride layers have not been reduced. A spacer silicon dioxide layer is deposited over the dielectric and then a polysilicon layer is deposited and formed into the shape of a the suspended microstructure.

Abstract: An electro-mechanical micromachined structure uses bumpers to prevent contact between structures at different potentials. A beam is connected to one or more anchors by flexible suspensions, which permit the beam to move along a predetermined axis relative to one or more plates. The suspension includes at least one bumper positioned so that the bumper will contact another part of the suspension before the beam contacts the plates. The bumper is made from the same material as the suspension, during the same processing step. The bumper is positioned to take advantage of shrinkage or expansion of the beam during processing which forces the bumper closer to its contact point then would otherwise be possible.

Abstract: Bipolar transistors and MOS transistors on a single semiconductor substrate involves depositing a single layer of polysilicon on a substrate, including complementary transistors of either or both types, and a method for fabricating same. The devices are made by depositing a single layer of polysilicon on a substrate and etching narrow slots in the form of rings around every bipolar emitter area, which slots are thereafter filler with an insulating oxide. Then, emitters and extrinsic base regions are formed. The emitters are self-aligned to the extrinsic base regions. An optical cladding procedure produces a surface layer of a silicide compound, a low resistance conductor. The resulting structure yields a high-performance device in which the size constraints are at a minimum and contact regions may be made at the top surface of the device.

Abstract: An all MOS single-ended to differential level converter including: first and second source follower circuits each including first and second PMOS semiconductors each having a drain, a source and a gate electrode; a current source commonly connected to the drain electrodes of the first and second PMOS semiconductors; an input circuit for providing to one of the gate electrodes a single-ended input signal and to the other an inverted single-ended input signal; and first and second load impedances connected to the source electrodes of the first and second PMOS semiconductors, respectively, for providing output analog differential signals at a level which is a function of the load impedances and current source magnitude.

Abstract: A cursor control system where the starting x-axis pixel position of the cursor pattern is determined by decoding the last two bits of the preloaded x-axis address (as determined by a manual control manipulated by the operator). This decoded data produces a signal for controlling the transmission gate multiplexer so as to determine the position where the cursor data stream is inserted into the video data stream.

Abstract: An accelerometer comprising a microfabricated acceleration sensor and monolithically fabricated signal conditioning circuitry. The sensor comprises a differential capacitor arrangement formed by a pair of capacitors. Each capacitor has two electrodes, one of which it shares electrically in common with the other capacitor. One of the electrodes (e.g., the common electrode) is movable and one of the electrodes is stationary in response to applied acceleration. The electrodes are all formed of polysilicon members suspended above a silicon substrate. Each of the capacitors is formed of a plurality of pairs of electrode segments electrically connected in parallel and, in the case of the movable electrodes, mechanically connected to move in unison. When the substrate is accelerated, the movable electrodes move such that the capacitance of one of the capacitors increases, while that of the other capacitor decreases.

Abstract: A leadframe that exhibits improved thermal dissipation and that can be incorporated into standard integrated circuit (IC) packages is provided by widening the inner lead portions with respect to the outer lead portions and extending them along a major surface of the IC. In the preferred embodiment, the wide inner lead portions cover at least 80 percent of the IC surface and also support the IC, eliminating the need for a leadframe paddle. The wide inner lead portions are more efficient at conducting heat away from the IC than prior "standard" width inner lead portions because of the increased thermal contact area between them and the IC. Heat from the IC is conducted to the outside of the package via the leads and into the circuit board on which the IC package is mounted. Added thermal dissipation is achieved by making the inner portion of a ground lead wider than the inner portion of any other lead.

Abstract: A circuit for selecting between two states and using the same pin as an input and an output. On power-up, the pin can be connected to either a grounded resistor (to select the first state) or the power supply (to select the second state). The input signal generates a logic select signal. The logic select signal selects between first and second logic formats. If the first format is selected, the pin is used to output a reference voltage for that format. If the second format is selected, the logic select signal also provides a disable signal, that prevents the reference voltage output from appearing on the pin.

Abstract: An IC amplifier having first and second cascaded stages formed by respective pairs of symmetrical complementary bipolar transistors followed by a unity gain buffer amplifier and provided with overall current feedback. The quiescent collector currents of the second amplifier stage are controlled by respective transconductance generators with respective complementary bipolar transistors connected in parallel relationship to the transistors of the second stage. The collector currents of the transconductance generators are fixed at the levels of respective reference current generators.

Abstract: A calibration system for an asymmetrical ramp generator system for a pulse width modulator wherein a current splitting circuit establishes a slew rate and a calibration level for the first ramp that is the same as the slew rate and the usable voltage range of the second ramp and wherein the first and second sets of ramps are matched so that calibration of the first set results in simultaneous calibration of the second set.

Abstract: A logic output stage that may be part of a circuit that provides the circuit user with the ability to select the type of digital electronic format for the digital signals output from the circuit. The logic output stage may include separate sections for processing signals so that they will have one of a plurality of digital electronic formats. Moreover, in cases where two or more digital electronic formats are very close, a single section may be used to process digital signals to have these formats.