Abstract: A random access memory (RAM) having an array of memory cells the signal lines to which are activatable by corresponding current sources. The memory is divided into "pages", and control pulses are produced to turn on the current sources involved in activating the signal lines to any page of memory cells being accessed and to turn off the remainder. The control pulses are directed through a pipelined pair of registers, and a look-ahead logic circuit examines the two pipelined control pulses identified as the "present" and "next" pulses. This logic circuitry serves to turn on the current sources for the page of memory to be accessed during the next clock time, and to maintain in an on state the current sources for the page of memory presently being accessed.

Abstract: A leadframe that exhibits improved thermal dissipation and that can be incorporated into standard integrated circuit (IC) packages is provided by increasing the thermal cross-section between the leadframe paddle and the lead fingers (leads) so that the leads are utilized for conducting a significant amount of heat away from the IC. A larger thermal cross-section can be achieved by making the shape of the paddle perimeter nonlinear to increase the surface area of its edge. In the preferred embodiment, the paddle perimeter has a "serpentine" shape and the inner ends of the leads are placed in close proximity to the paddle perimeter and are shaped to substantially follow its serpentine shape. The shaped paddle and lead ends increase the thermal cross-section between the paddle and the leads, resulting in improved thermal conduction. The leads conduct the heat to the outside of the package, where it is dissipated into the circuit board on which the leadframe package is mounted.

Abstract: Process for making an integrated-circuit (IC) chip with junction-isolated complementary bipolar transistors. In this process an N-well is formed in a P-type substrate. P-type dopant is implanted in the N-well to become a sub-collector for a pnp transistor. N-type dopant is implanted in the substrate in a location laterally displaced from the N-well to become a sub-collector for an npn transistor. N-type material is implanted in the N-well to begin the formation of an isolation wall for the pnp transistor. A P-type epitaxial (epi) layer then is grown over the P-type substrate. N-type material is implanted in the epi layer to complete the isolation wall for the pnp transistor, and to complete the collector for the npn transistor. P-type and N-type material also is implanted in the P-type epi layer to form the bases and emitters for the npn and pnp transistors.

Abstract: Open-loop differential amplifiers (120, 140) are disclosed which have accurate and stable gain. The gain of these amplifiers is substantially insensitive to the effects of small-signal emitter resistance r.sub.e, current gain .beta. and Early voltage V.sub.A. Thus, their gain can be accurately set by resistance ratios which makes them particularly useful in integrated circuits. These advantages are obtained with an output differential pair (67) that has cross-coupled base and collector terminals. In addition, resistors (141, 143, 148, 150) and a current source (146) associated with this differential pair are related to like elements (27, 28, 24, 25 and 26) that are associated with an input differential pair (21) by disclosed numerical ratios, e.g., the nominal gain G of the amplifier. Versions of the amplifiers can be adapted for use as a residue amplifier (162) in a subranging A/D converter (160).

Abstract: A method and apparatus for phase locking to an input signal and outputting a sigma-delta modulated control signal. The method and apparatus of the present invention provide a sigma-delta modulated control signal which can be utilized by any one of a decimator for decimating a digital data at a first data rate to a digital data at a second data rate and an interpolator for interpolating a digital data at a first data rate to a digital data at a second data rate. The decimator and the interpolator can be utilized in any one of an analog-to-digital converter, a digital-to-analog converter and a digital-to-digital converter. In one embodiment, a period of the input signal is determined and fed to a phase-locked loop which includes a sigma-delta modulator for providing the sigma-delta modulated control signal. The phase-locked loop also includes a phase detector for determining a phase and a frequency-difference between the input signal and a conversion signal generated by the phase-locked loop.

Abstract: A current mode VCA includes a negative feedback architecture around a gain core stage. An input signal is injected as a differential current into the signal path and is converted to a differential voltage by a transresistance stage having a dynamic impedance. The differential voltage is applied to a transconductance stage which limits the VCA's high frequency gain and stabilizes the feedback loop. The transconductance stage supplies a differential drive current to the gain core stage, which produces two differential output currents that sum to the differential drive current. The fraction of the drive current provided to each output current is controlled by the application of a control signal to the gain core stage. A current-to-voltage converter produces an output voltage in response to the output current.

Abstract: An intrinsic R2R resistance ladder digital to analog converter (DAC) includes a plurality of matched semiconductor ladder switches, one in each of the R and 2R legs of the R2R ladder. The ON resistance of each semiconductor switch being matched to constitute the resistance ladder of the DAC; the ladder switches being operated in response to the digital signal input to the DAC; a reference circuit including a reference semiconductor switch matched with the ladder switches responsive to a reference current to generate a reference voltage; and a voltage follower circuit for monitoring the reference voltage and adjusting the current through the ladder switches to match the voltage at each ladder switch with the reference voltage for precisely fixing the DAC analog output current as a proportion of the reference current in dependence upon the operation of the ladder switches by the digital input signal.

Abstract: A double-folded cascode operational amplifier capable of operating with rail-to-rail common mode inputs includes two differential input transistor pairs of opposite conductivity, with an associated current source and input resistor pair for each pair of input transistors. Its gain stage includes two interconnected pairs of folded cascode gain transistors that are connected to the two pairs of input resistors so that a change in the differential input signal produces a corresponding change in the gain stage output via the resistors. An output stage includes transistor-resistor circuitry to bias a pair of output transistors in opposite directions and produce a net amplifier output at their junction. The gain transistor voltages are balanced by a voltage shifting circuit to inhibit input voltage offsets.

Abstract: A bipolar micro-power rail-to-rail operational amplifier has a low complexity output stage that provides a high ratio of load current to no load idle current. The output stage includes first and second output transistors of opposite conductivities whose current circuits are connected in series at the output terminal between high and low voltage supplies. A control transistor responds to the drive voltage at its base by modulating the base-emitter voltages of the first output transistor and a gain transistor in opposite directions to modulate their respective output and gain currents. A regenerative current source supplies current to the gain transistor by returning the gain current in a regenerative feedback loop to its emitter so that the current source idles at a low gain current but is capable of supplying much higher gain currents.

Abstract: A bipolar micro-power rail-to-rail operational amplifier has a low complexity output stage that provides a high ratio of load current to no load idle current. The output stage includes first and second output transistors of opposite conductivities whose current circuits are connected in series at the output terminal between high and low voltage supplies. A control transistor responds to the drive voltage at its base by modulating the base-emitter voltages of the first output transistor and a gain transistor in opposite directions to modulate their respective output and gain currents. A regenerative current source supplies current to the gain transistor by returning the gain current in a regenerative feedback loop to its emitter so that the current source idles at a low gain current but is capable of supplying much higher gain currents.

Abstract: An electrostatic discharge (ESD) protection circuit formed on a semiconductor substrate includes a first stage clamping circuit and a second stage clamping circuit separated by a dissipative circuit. The first and second stage clamping circuits are designed to absorb and dissipate the high and low energy ESD, respectively. The first clamping circuit has a self-regulated current mechanism capable of diverting the electrical current generated by an ESD from a high current density region to a low current density region within the semiconductor substrate, and simultaneously lowers the ESD induced voltage for safe protection.

Abstract: An IC temperature sensor with a programmable offset generates an output voltage V.sub.o over a desired temperature range that is a PTAT voltage V.sub.PTAT shifted by an offset voltage V.sub.off. A band gap cell generates a basic PTAT voltage across a first resistor to produce a PTAT current I.sub.PTAT. A second resistor is connected from the first resistor to a reference voltage terminal to provide voltage gain. A third resistor is connected across the base-emitter junction of a transistor which is connected from the top of the second resistor to an output terminal at which V.sub.o is generated. The transistor's base-emitter voltage provides a portion of V.sub.off. The third resistor reduces the portion of I.sub.PTAT that flows through the second resistor to provide the remaining portion of V.sub.off. A current source is positioned between the transistor's emitter and the reference voltage terminal to supply its emitter current and the current for the third resistor. The offset voltage V.sub.

Abstract: A random access memory (RAM) having an array of memory cells the signal lines to which are activatable by corresponding current sources. The memory is divided into "pages", and control pulses are produced to turn on the current sources involved in activating the signal lines to any page of memory cells being accessed and to turn off the remainder. The control pulses are directed through a pipelined pair of registers, and a look-ahead logic circuit examines the two pipelined control pulses identified as the "present" and "next" pulses. This logic circuitry serves to turn on the current sources for the page of memory to be accessed during the next clock time, and to maintain in an on state the current sources for the page of memory presently being accessed.

Abstract: A leadframe that exhibits improved thermal dissipation and that can be incorporated into standard integrated circuit (IC) packages is provided by increasing the thermal cross-section between the leadframe paddle and the lead fingers (leads) so that the leads are utilized for conducting a significant amount of heat away from the IC. A larger thermal cross-section can be achieved by making the shape of the paddle perimeter nonlinear to increase the surface area of its edge. In the preferred embodiment, the paddle perimeter has a "serpentine" shape and the inner ends of the leads are placed in close proximity to the paddle perimeter and are shaped to substantially follow its serpentine shape. The shaped paddle and lead ends increase the thermal cross-section between the paddle and the leads, resulting in improved thermal conduction. The leads conduct the heat to the outside of the package, where it is dissipated into the circuit board on which the leadframe package is mounted.

Abstract: In one band gap reference cell, first and second transistors have the bases thereof coupled together. A first supply voltage line is operatively connected to the collectors of the transistors and a second supply voltage line is operatively connected to the emitters of the transistors. The voltage supply lines produce a current proportional to temperature when the device is operating. A first resistor is connected between the emitter of one of the transistors and the second supply line. A third transistor has the base thereof coupled to the bases of the first and second transistors. A current is established in a curve-compensation resistor which is equal to the sum of the currents in the first and second transistors less a nonlinear portion which arises from variations in V.sub.BE with respect to temperature. A second resistor is connected across the base-emitter junction of one of the transistors. A current complementary to temperature is established in the resistor when the device is operating.

Abstract: A digitally controlled calibration circuit for a DAC includes a primary DAC having a first reference current input, a second input for receiving a digital signal representative of the DAC conversion factor, and an output for providing the analog signal; a secondary calibration DAC has associated with it a reference network connected to a first input of the secondary DAC for conducting a reference current, and a device for connecting the output of the secondary DAC to the reference network, the second DAC includes a second input for receiving a digital signal for adjusting the output of the secondary DAC fed back to the reference network for adjusting the reference current; and a device for interconnecting the reference current with the first reference current input of the primary DAC for digitally controlling the reference current input of the primary DAC for digitally controlling the reference current to that primary DAC and digitally effecting calibration of the primary DAC.

Abstract: The invention is a method and apparatus for electrostatic potential sensing by using electromechanical microstructures. The mechanical microstructure may be fabricated by either surface micromachining or bulk-micromachining. The sensor comprises a movable plate which is movable in the lateral dimension and which is suspended from and above a substrate bearing an isolated electrically conductive layer. The layer acts as the sensor electrode and is brought in contact with or near the object the electrostatic potential of which is to be sensed. The movable plate is suspended between two fixed, suspended and cantilevered plates. The three suspended plates collectively form two capacitors with the two fixed plates comprising the first plate of first and second capacitors and the movable plate comprising the second plate of both capacitors.

Abstract: Gain linearity problems caused by impact ionization in a active MOS device are avoided by connecting an MOS shield device in series with the active MOS device so that the overall supply voltage is split across two devices, keeping both devices in a region of operation well below where impact ionization becomes a significant problem. The gate of the MOS shield device is maintained at a voltage proportional to its drain voltage, thereby keeping the device in the saturation mode and avoiding an abrupt mode change associated with prior art shield circuits.

Abstract: A circuit for minimizing electrostatic forces in capacitance-based sensor circuits. A sensor includes a movable mass that forms the center electrode of two differential capacitors, a sensing differential capacitor and an actuator differential capacitor. The other two electrodes of each differential capacitor are fixed. Oppositely phased high-frequency carrier signals are applied to the fixed electrodes of the sensing capacitor and biasing signals are applied to the fixed electrodes of the actuator capacitor. When a force is applied to the sensor, the capacitance of the sensing capacitor changes and the carrier signal, with its amplitude and phase modulated in accordance with the magnitude and direction of the force, appears on the movable mass. The signal on the mass is fed back to the fixed electrodes of the sensing capacitor to minimize electrostatic forces between the electrodes of the sensing capacitor.

Abstract: A method and apparatus for digital-to-analog conversion using sigma-delta modulation of the temporal spacing between digital samples are provided. The method and apparatus include sigma-delta modulation of the time-base such that errors produced by non-uniform sampling are frequency-shaped to a high frequency region where they are reduced by conventional filtering techniques. In one embodiment, an oversampling modulator receives digital input samples and, responsive to a noise-shaped clock signal, modulates the digital input samples to produce modulated samples at an oversampling rate. The oversampling rate preferably is equal to an oversampling ratio times a preselected input sample rate. A DAC, coupled to the modulator, converts the modulated samples to an analog signal.