Abstract: An ESD protective clamp device comprised of a two-terminal diode formed in an isolated chip cell. The lower part of this chip cell region contains a buried layer of silicon with P-type dopant, and the upper part is an epitaxial layer also with P-type dopant. An annular (ring-shaped) anode plug segment is formed at the outer reaches of the epitaxial layer with P+ doping. At the interior central region is an N-type plug circular in horizontal cross-section and concentric with the annular plug. This central plug serves as the cathode. Electrical connections are made to anode and cathode to provide interconnection with an IC circuit with a MOM capacitor to be protected.

Abstract: An asynchronous digital sample rate converter includes a random access memory for storing input data values and a read only memory for storing a reduced set of interpolation filter coefficients. Input data is written to the random access memory at the input sample rate. Output samples are provided from a multiply/accumulate engine which given a stream of input data and filter coefficients produces an output sample upon request at the output frequency. The initial address for reading input data from the random access memory, and the addresses for coefficients from the read only memory are provided by an auto-centering scheme which is a first order closed loop system with a digital integrator fed by an approximation of the input to output sample rate ratio. This auto-centering scheme may include a feed forward low pass filter to cancel steady state error, and an interpolated write address to reduce noise.

Abstract: An asynchronous digital sample rate converter includes a random access memory for storing input data values and a read only memory for storing a reduced set of interpolation filter coefficients. Input data is written to the random access memory at the input sample rate. Output samples are provided from a multiply/accumulate engine which given a stream of input data and filter coefficients produces an output sample upon request at the output frequency. The initial address for reading input data from the random access memory, and the addresses for coefficients from the read only memory are provided by an auto-centering scheme which is a first order closed loop system with a digital integrator fed by an approximation of the input to output sample rate ratio. This auto-centering scheme may include a feed forward low pass filter to cancel steady state error, and an interpolated write address to reduce noise.

Abstract: A multi-phase, multi-access pipeline memory system includes a number, n, of processors; a pipeline memory including a latch; and a bus for interconnecting the processors and pipeline memory; a clock circuit responsive to a system clock signal divides the system clock signal into n phases for providing multiple clock signals corresponding to the n phases of the system clock signal for operating each processor to allow data and address to be transferred only during its assigned phase thereby enabling the memory and each processor to operate at the system clock rate while allowing n accesses to the memory during each system clock signal period, one access for each processor.

Abstract: A servo system for controlling the position of a read/write head in a disk drive is provided. The servo system includes two input terminals for sequentially receiving a plurality of input signal AC voltage bursts of a burst pattern, wherein the input signal bursts include positional information of the head. Demodulation circuitry, coupled to the input terminals, sequentially demodulates each input signal burst and provides a demodulated signal for each burst. The demodulation circuitry includes translation circuitry, coupled to the input, for sequentially translating each input voltage burst to a translated current. A rectifier circuit, coupled to the translation circuitry, including an absolute value circuit and a current mirror circuit, sequentially rectifies each translated current and produces a driving signal. An integrator, coupled to the rectifier circuit, sequentially integrates each driving signal. The integrator includes an integration capacitor which is sequentially charged by each driving signal.

Abstract: A CMOS input circuit that has a first inverter stage for comparing non rail-to-rail digital input voltages to a threshold voltage, and producing inverted CMOS output voltages is disclosed. The inverted output voltages are approximately equal to a low CMOS supply voltage plus an offset voltage and a high CMOS supply voltage. The inverter includes PMOS and NMOS transistors that are connected to receive a common input voltage at their gates and to have a common drain current. The PMOS' source is connected to the high supply voltage, and the NMOS' source is connected through a voltage drop circuit element to the low supply voltage. The inverted output voltage is produced at the connection of the PMOS and NMOS transistors' drains. The NMOS and PMOS transistors have gate width and length parameters W.sub.N, L.sub.N and W.sub.P, L.sub.P, respectively. The ratio ##EQU1## is selected so that the threshold voltage is set between the maximum low and minimum high input signals for a desired range of high supply voltages.

Abstract: An accelerometer comprising a microfabricated acceleration sensor and monolithically fabricated signal conditioning circuitry. The sensor comprises a differential capacitor arrangement formed by a pair of capacitors. Each capacitor has two electrodes, one of which it shares electrically in common with the other capacitor. One of the electrodes (e.g., the common electrode) is movable and one of the electrodes is stationary in response to applied acceleration. The electrodes are all formed of polysilicon members suspended above a silicon substrate. Each of the capacitors is formed of a plurality of pairs of electrode segments electrically connected in parallel and, in the case of the movable electrodes, mechanically connected to move in unison. When the substrate is accelerated, the movable electrodes move such that the capacitance of one of the capacitors increases, while that of the other capacitor decreases.

Abstract: A voltage regulator is capable of providing multiple fixed outputs plus a user-selected output by the use of a window comparator circuit that produces one of three different possible outputs, depending upon whether an input control signal is above, below or within the window voltage range. Two of the outputs operate different switches within a feedback circuit for a multiplying operational amplifier, causing the amplifier to produce different regulated output levels depending upon which switch is operated. The third window output disables the operational amplifier and establishes a mode in which the regulated output is set by an external feedback circuit for another operational amplifier, with the external circuit connected across the circuit's input and output terminals.

Abstract: A current mirror circuit and method of generating an output current at an output node which is proportional to an input current applied to an input node. The circuit operates to receive the input current and develops a reference voltage. The reference voltage is converted to a reference current which is proportional to the input current and is applied to a high impedance node. A feedback network is coupled to said high impedance node and includes an output device driven by the high impedance node and which provides the output current to the output node. The feedback network is operable for forcing current generated by said feedback network to the high impedance node to be equal to the reference current.

Abstract: A transimpedance amplifier for an optical receiver includes an integrator circuit for receiving a current input from a photodetector; an integrator capacitance between the input and output of the integrator circuit; a gain stage responsive to the output of the integrator circuit for providing an output voltage representative of the current input to the integrator circuit; and a feedback resistance connected between the output of the gain stage and the input of the integrator circuit for establishing the nominal gain of and in conjunction with the integrator circuit for setting the nominal bandwidth of the transimpedance amplifier; the gain stage may have a gain greater than unity for increasing the bandwidth by the factor of the gain and the gain stage may include a trimmable resistance for adjusting the gain both below and above unity.

Abstract: A quasi-passive switched capacitor (SC) delay line includes a predetermined number (N) of passive SC delay stages and an amplifier. Each delay stage includes a first transistor having a control terminal for receiving a clock phase, an input terminal for receiving an input signal, and an output terminal, a second transistor having a control terminal for receiving a different clock phase, an input terminal connected to the output terminal of the first switching device, and an output terminal coupled to the amplifier input, and a capacitor coupled between the output terminal of the first transistor and a common supply voltage. The control terminal of each first transistor receives a unique clock phase and the control terminal of the second transistor of the same stage being receives a different clock phase wherein the clock phase received by the second transistor is delayed by two clock cycles from the clock phase received by the first transistor.

Abstract: A switched-capacitor DAC system includes two switched-capacitor DACs and a load circuit. The switched-capacitor filter of the first DAC samples a reference voltage source, which produces a reference voltage, at a first rate and the switched-capacitor filter of the second DAC samples the reference voltage source at a second rate, greater than the first rate. The load circuit samples the reference voltage source at a rate such that the level of the reference voltage is the same each time a sample is taken. The load circuit effectively equates the sampling of the two filters and substantially eliminates problems related to gain errors and low frequency quantization noise.

Abstract: A digital filter includes a pre-filter cascaded to a low pass filter. The pre-filter has a transfer function providing generally increasing attenuation with increasing frequency above a cutoff frequency. The low pass filter has a transfer function providing substantially decreasing attenuation with increasing frequency above the cutoff frequency. The low pass filter is an FIR filter including coefficients restricted to the set {+1, 0 and -1}. The filters are preferably implemented using simple hardware such as addressable read/write RAM, digital adder/subtracters, and registers. Alternatively, the addressable RAM can be replaced with shift registers. Such a filter is easily and economically implemented and has a favorable overall frequency response characteristic. The filter is, therefore, well suited for use in many digital applications and, in particular, for use as a decimation filter in an oversampled, multi-bit, high order analog-to-digital converter system.

Abstract: A digital-to-analog converter including a plurality of binarily-weighted stages each incorporating a differential switch-pair circuit which includes two matched bipolar switch transistors the bases of which are driven by a corresponding pair of complementary signal sources. Two additional switches are included in this circuit, with each such switch being connected between a respective signal source and its corresponding transistor control electrode. These two switches are both opened before the clock-controlled activation of the complementary signal sources. A short time after such activation, sufficient to assure that the complementary signal voltages have stabilized at their new values, the two additional switches are reclosed simultaneously by a single control signal so as to effect synchronized switchover of the two switch transistors at that instant.

Abstract: A back gate bias voltage is applied to the underside of a lateral bipolar transistor to desensitize a portion of the collector-base depletion region to changes in the collector-base voltage. Emitter-collector current flows through an active base region bypassing the portion of the collector-base depletion region that remains sensitive to the collector bias. This allows for a control over the charge in the active base region by the back gate bias, generally independent of the collector-base bias. The transistor is preferably implemented in a silicon-on-insulator-on-silicon (SOIS) configuration, with the back gate bias applied to a doped silicon substrate. The base doping concentration and the thickness of the underlying insulator are preferably selected to produce an inversion layer in the base region adjacent the insulating layer, thereby reducing the collector access resistance.

Abstract: A diode-connected transistor device for IC protection against electrostatic discharge (ESD) that functions as a transistor in the active region during an ESD event. The device cell includes an annular collector at the outer reaches of the cell, a circular base diffusion concentric with the collector, and an annular emitter near the outer edge of the base. The base and emitter regions are connected together by metallization external to the transistor cell. With the base contact enclosed by the annular emitter, during an ESD spike the initial reverse bias current flow is from the collector, under the emitter diffusion and out of the base contact. Eventually, as the magnitude of the ESD spike increases, the reverse biased current becomes sufficient to locally forward bias the base-emitter junction changing the primary ESD current path from collector to base, to collector to emitter, thus lowering the ESD current density in the active base-collector junction.

Abstract: A frequency-responsive integrated circuit (IC) for determining when the frequency of a clock pulse input signal is below a predetermined threshold level, the IC including a capacitor charged up at a nearly constant rate by a current source. If the capacitor voltage reaches one-third of the DC power voltage, and input pulses are received, the capacitor is discharged to start another charge-up cycle. If no input pulses were received, the capacitor continues to charge up until its voltage reaches two-thirds of the DC power voltage, at which point an output signal is produced indicating that the input frequency is below the predetermined threshold level.

Abstract: An integrated-circuit (IC) chip formed with a fault-protected switch comprising three MOS transistors in series. An additional MOS transistor is formed adjacent the center one of the three transistors, and is arranged such that the gates of the two transistors are connected together, the source electrodes of the two transistors are connected together, the backgates form a common region, and the drain of the additional transistor is connected to those backgates.

Abstract: Bipolar transistors and MOS transistors on a single semiconductor substrate involves depositing a single layer of polysilicon on a substrate, including complementary transistors of either or both types, and a method for fabricating same. The devices are made by depositing a single layer of polysilicon on a substrate and etching narrow slots in the form of rings around every bipolar emitter area, which slots are thereafter filled with an insulating oxide. Then, emitters and extrinsic base regions are formed. The emitters are self-aligned to the extrinsic base regions. An optional cladding procedure produces a surface layer of a silicide compound, a low resistance conductor. The resulting structure yields a high-performance device in which the size constraints are at a minimum and contact regions may be made at the top surface of the device.

Abstract: CRT control apparatus for use in high-resolution graphic display equipment of the type including a frame buffer having storage banks for storing digital signals representing the color intensities of red, green and blue colors of pixels on the CRT screen. The control apparatus is formed in a single MOS integrated-circuit (IC) chip which incorporates three multiplexers for the three 8-bit sets of color digital signals from the frame buffer. The 8-bit outputs of the multiplexers are directed to digital-signal-transformation devices which, in response to each 8-bit signal, produce a corresponding 10-bit signal incorporating the color-intensity information of the original 8-bit signal, and also incorporating a gamma correction factor for the particular intensity represented by the original 8-bit signal. The 10-bit signals are directed to 10-bit DACs, one for each color, to produce corresponding analog control signals for the corresponding electron guns of the CRT.