Abstract: A method for forming sub-micron sized bumps on the bottom surface of a suspended microstructure or the top surface of the underlying layer in order to reduce contact area and sticking between the two layers without the need for sub-micron standard photolithography capabilities and the thus-formed microstructure. The process involves the deposition of latex spheres on the sacrificial layer which will later temporarily support the microstructure, shrinking the spheres, depositing aluminum over the spheres, dissolving the spheres to leave openings in the metal layer, etching the sacrificial layer through the openings, removing the remaining metal and depositing the microstructure material over the now textured top surface of the sacrificial layer.

Abstract: A multistage pipelined algorithmic A/D converter digitally calibrated to avoid errors due to charge injection, offset and capacitor mismatch. To perform this calibration, measurements are made at the converter to determine the degree of capacitor mismatch for each stage to be calibrated. In the embodiment disclosed, only one stage is calibrated. The remaining stages of the converter are employed to develop the digital calibration data for the stage being measured. This calibration data is stored in a memory forming part of the converter. The stored data is thereafter used during each conversion to cancel the errors due to capacitor mismatch.

Abstract: A method for fabricating a micromechanical device and a semiconductor circuit on a substrate includes the steps of forming the micromechanical device on a device area of the substrate, the micromechanical device being embedded in a sacrificial material, selectively depositing a planarization layer on the substrate in a circuit area thereof, forming the semiconductor circuit on the planarization layer in the circuit area and removing the sacrificial material from the embedded micromechanical device. In a preferred embodiment, the planarization layer is an epitaxial silicon layer. A protective cap may be formed over the micromechanical device, so that it is completely encapsulated and is thereby protected against particulate contamination.

Abstract: A method and apparatus for digital-to-digital conversion using sigma-delta modulation of the temporal spacing between digital samples. The method and apparatus of the present invention provides for sigma-delta modulation of the time base such that noise produced by non-uniform sampling are frequency-shaped to a region (i.e., shifted to higher frequencies) where it can be removed by conventional filtering techniques. In one embodiment, the digital data is interpolated by fixed ratio and then decimated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the incoming digital data stream. Thereafter, the digital data is interpolated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the digital data to be output by the converter and then decimated by a fixed ratio. The first and second frequency signal selection numbers are modulated using n-th order m-bit sigma-delta modulators.

Abstract: Defects in the manufacturing of IC devices are analyzed by testing the devices for defects, generating a serial digital data bitstream upon which the test result for each device is encoded in succession, and operating upon the data bitstream to analyze the device defects. This allows for the use of rapid and reliable digital signal processing techniques to perform the analysis. The types of analyses that can be performed include the determination of non-random yields to distinguish random from systematic defects, comparisons with signature defect patterns that correspond to various systematic faults, and yield predictions for other circuits manufactured with a similar process but having a different critical circuit area. An improved windowing technique is used to determine non-random defects, in which normalized defect counts are obtained and compared for various window sizes.

Abstract: The number of resistors and switches required for a voltage-scaling digital-to-analog converter (DAC) is greatly reduced by segmenting the voltage decrementing resistor string into two separate outer strings and an inner string. The outer strings decrement a full-scale voltage in accordance with the most significant bits (MSBs) of the input digital signal, while the inner string decrements the least significant bits (LSBs); alternately, the outer strings can decrement the LSBs and the inner string the MSBs. Opposite ends of the inner string are connected to corresponding points on the two outer strings through passive switched taps on the outer strings that allow the DAC to function as a potentiometer or rheostat, and "slide" up and down along the two outer strings as the input digital signal varies. An analog output is tapped from a selected point on the inner string whose voltage elevation is controlled by the switching of the outer strings.

Abstract: A biquad switched capacitor filter is preferably utilized as the output filter in a sigma delta digital-to-analog converter. The switched capacitor filter uses a cross-coupled switched capacitor circuit which delivers charge to the capacitors on both phases of the clock. As a result, the sizes of the capacitors can be reduced by a factor of two, while delivering the same charge as a single sampling circuit. By using the cross-coupled switching circuit everywhere in the filter, the sensitivity to capacitor mismatches is substantially reduced. The clock phases applied to the stages of the filter are alternated so that there is a one clock cycle delay around each loop containing two filter stages, thereby insuring the stability of the filter.

Abstract: A phase locked loop system or other second order feedback system whose natural frequency scales with its output and whose damping factor remains constant includes a filter circuit having a scaling channel for scaling the error, an integrating channel for integrating the error, and a summing circuit for combining the scaled error and integrated error; an integrator circuit responsive to the summing circuit to produce an output signal, the gain of the integrator circuit being proportional to its output signal; and a control circuit for controlling the gain of the integrating channel proportional to the output signal and maintaining constant the ratio of and scaling the product of the unity gained frequency and the zero frequency of the feedback system to keep constant the damping factor and to scale the natural frequency of the feedback system with the output signal, respectively.

Abstract: A test socket for a surface mount IC chip includes an array of double-ended spring contacts that extend out from opposite sides of a substrate, with a positioning frame on top of the substrate for aligning a chip and its leads with the upper contact heads. The spring contacts preferably have hollow elongate bodies with contact heads extending out from opposite sides under an internal spring bias. The socket can be formed from two laminates which have a series of aligned openings for the spring contacts, with expanded midsections on the spring contacts press-fit into the laminate openings and thereby securing holding the laminates together. A standoff on the upper socket surface vertically positions the IC chip, and provides the proper contact pressure between its leads and the spring contacts. The test socket can be removably mounted to a PC test board, with a releasable clamping device such as an air cylinder used to hold a chip to be tested in place within the socket.

Abstract: A method and apparatus for digital to analog conversion using sigma-delta modulation of the temporal spacing between digital samples. The method and apparatus of the present invention provides for sigma-delta modulation of the time base such that errors produced by non-uniform sampling are frequency-shaped to a region (i.e., shifted to higher frequencies) where they can be removed by conventional filtering techniques. In one embodiment, the digital data is interpolated by a fixed ratio and then decimated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the incoming digital data stream. The frequency signal selection number is modulated using an n-th order m-bit sigma-delta modulator. Data thus emerges from the interpolation/decimation process at the clock rate of the n-th order m-bit sigma-delta modulator.

Abstract: An oscillator including two gm/C stages is disclosed. Each gm/C stage includes a differential pair of transistors, a capacitor, and a tunable current source. Alternatively, multi-tanh n-tuplets can be used in place of the differential pairs in the gm/C stages to increase the linearity of the gm/C stage. The gm/C stages include a pair of input terminals, a pair of output terminals, and a pair of common-mode terminals. The two gm/C stages are interconnected in a feedback loop to form a quadrature oscillator. A common-mode biasing circuit is coupled a supply voltage and each pair of common-mode terminals for biasing the respective gm/C stage. The common-mode biasing circuits can include: current mirrors, diode pairs, and even resistors. An optional start-up circuit can be coupled to each gm/C stage to ensure start-up of the associated gm/C stage.

Abstract: A detector cell for a logarithmic includes a differential pair of inputs across which a input signal V.sub.0 is applied across. The detector cell also includes a pair of differential outputs. The detector cell is comprised of three transistors Q4, Q5 and Q6. Resistors are coupled between the bases of adjacent transistors. The resistors form a voltage divided across which the input signal V.sub.0 is divided. The emitters of the three transistors are coupled to a current source, which sends a predetermined amount of current Ihd D. The collectors of the first and third transistors are coupled together to form a first differential input of the differential input pair. The collector of the second transistor alone forms the second differential input of the pair. The emitter area of the second transistor is ratioed with respect to the first and third so that a current I.sub.1 flowing through the first differential output is equal to a current I.sub.

Abstract: A programmable gain amplifier including first and second gain elements are connected by an impedance selector which allows programmability of the gain of both gain elements. The impedance selector is connected in series with the output of the first gain element. The impedance selector places an impedance in the feedback path of the first gain element or the input path of the second gain element. Errors introduced in the signal path due to the switches are attenuated by the open loop gain of the first gain element. The gain may be equally divided between both stages of the amplifier to allow for optimum band width. Optimum noise performance may be obtained by placing most of the gain in the first stage. An instrumentation amplifier may also be made which further includes a third gain element connected to the gain element with a second impedance selector in a manner similar to the connection of the first gain element to the second gain element.

Abstract: A package for housing integrated circuit chips that provides EMF shielding and thermal protection, while conforming to an industry recognized package outline, is provided. This EMF shielding and thermal protection is achieved by providing an electrically conductive heat sink that provides heat dissipation and that, together with a separate electrically conductive layer, also acts as an EMF shield. The heat sink contains a recess and is positioned against the conductive layer with the recess facing the conductive layer. The integrated circuit (IC) resides inside the cavity formed by the heat sink and conductive layer and is protected from EMF by the heat sink and conductive layer. The heat sink, electrically conductive layer and IC are then encapsulated in an electrically insulating molding compound that is molded to an industry recognized package outline. Additional ICs can be housed in this package by attaching them to the side of the electrically conductive layer opposite the heat sink.

Abstract: A method and apparatus for analog to digital conversion using sigma-delta modulation of the temporal spacing between digital samples. The method and apparatus of the present invention provides for sigma-delta modulation of the time base such that errors produced by non-uniform sampling are frequency-shaped to a region (i.e., shifted to higher frequencies) where they can be removed by conventional filtering techniques. In one embodiment, digital data is interpolated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the digital data to be output by the converter and then decimated by a fixed ratio. The frequency selection signal is modulated using an n-th order m-bit sigma-delta modulator. Data thus emerges from the interpolation/decimation process at the sample rate selected by the n-th order m-bit sigma-delta modulator.

Abstract: A self-aligned capacitor structure and method of making it includes an insulating support substrate with the capacitor disposed on the insulating substrate with a first conducting extending across the capacitor in the first dimension. The capacitor includes a first electrode interconnected with the first conductor, a second electrode supported by the substrate and interconnected with the second conductor, and a dielectric medium between the first and second electrodes. The first and second electrodes being coterminous in both directions in the first dimension for eliminating parasitic capacitance between the first conductor and the second electrode.

Abstract: An overvoltage protection circuit protects against saturation and damage of sensitive circuitry elements. The protection circuit includes an out-of-range detector which compares an input signal to reference levels to determine if it is within a predetermined range of acceptable inputs. If the input is determined not to be within this range, a control circuit substitutes a supplemental signal within the range for the input signal. Digital correction can be provided to correct the output of the sensitive circuit element while the supplemental signal is being substituted. Numerous circuit designs may be used to implement the protection scheme.

Abstract: An integrated circuit metal-oxide-metal capacitor and method of making it which involves a support layer; a first conductive electrode on the support layer; a dielectric film on the first conductive electrode; a second conductive electrode disposed on the dielectric film and formed from the first level metallization interconnect layer of the integrated circuit; an interlevel dielectric layer; a first contact via extending through the interlevel dielectric layer and the dielectric film to the first conductive electrode; a second contact via extending through the interlevel dielectric layer to the second conductive electrode; and first and second terminals formed from the second level metallization interconnect layer of the integrated circuit contacting the first and second vias, respectively.

Abstract: An SOI/DI IC chip including a handle wafer in the form of a section of silicon substrate contiguous with the layer of insulation beneath the silicon slice containing the device regions separated by trenches filled with low-conductivity polysilicon dielectric. One of the trenches is etched through the layer of insulation, and the polysilicon in that trench is doped to provide desired electrical conductivity to establish electrical contact with the handle wafer. Metallization is applied over the top of this one trench to make possible electrical connection to the handle wafer from above the chip by use of conventional wiring techniques.

Abstract: A switched-capacitor auto-zero integrator includes and integrator circuit and a correction circuit. The integrator circuit may be any circuit including an operational amplifier having an input line and an output line, an input capacitor coupled to be charged by an Input voltage, an integrating capacitor coupled to the output line, and at least one integrating switch operable during an integrating time interval to connect the input capacitor to the integrating capacitor such that the integrating capacitor is charged to compensate for charge of the input capacitor. The correction circuit includes an offset capacitor coupled to the input line and at least one correction switch operable in an auto-zero sub-interval: and a correction sub-interval.