Abstract: A gain stage for use in an amplifier which provides a rail-to-rail output signal. The gain stage includes a first transistor having a base, an emitter and a collector, the base being coupled to an input signal applied to the gain stage and the emitter being coupled to a first source of operating potential; a second transistor having a base, an emitter and a collector, the collector being coupled to the collector of the first transistor for providing the output signal, the emitter being coupled to a second source of operating potential; and a third transistor having a base, an emitter and a collector, the emitter being coupled to the input signal, the base being coupled to a bias voltage, and the collector being coupled to the second operating potential and the base of the second transistor for providing a drive signal thereto allowing the output signal to swing substantially between the first and second sources of operating potential.

Abstract: CRT control apparatus for use in high-resolution graphic display equipment of the type including a frame buffer having storage banks for storing digital signals representing the color intensities of red, green and blue colors of pixels on the CRT screen. The control apparatus is formed in a single MOS integrated-circuit (IC) chip which incorporates three multiplexers for the three 8-bit sets of color digital signals from the frame buffer. The 8-bit outputs of the multiplexers are directed to digital-signal-transformation devices which, in response to each 8-bit signal, produce a corresponding 10-bit signal incorporating the color-intensity information of the original 8-bit signal, and also incorporating a gamma correction factor for the particular intensity represented by the original 8-bit signal. The 10-bit signals are directed to 10-bit DACs, one for each color, to produce corresponding analog control signals for the corresponding electron guns of the CRT.

Abstract: An analog-to-digital converter (ADC) having two cascaded A/D stages of the parallel type wherein the analog signal is compared with a set of threshold reference voltages. The first stage develops a set of most-significant bits and produces two analog residue signals: a normal residue corresponding to the difference between the analog input and the threshold voltage below the analog input, and a second residue corresponding to the difference between the analog input and the threshold voltage above the analog signal level. These two residue signals are amplified and directed to the second A/D stage. The sum of the residue signals equals one LSB of the first A/D stage, so that the two residues supply to the second stage information about the quantization error of the previous stage as well as the quantization step size to be used to define full-scale at the second stage.

Abstract: A parasitic capacitance cancellation circuit for a direct bonded silicon-on-insulator integrated circuit includes one or more transistors fabricated silicon-on-insulator; a silicon substrate region outside the transistor(s) having a parasitic capacitance to be cancelled; a bootstrap terminal connected to the region outside the transistor(s); and a unity gain buffer responsive to the output of the transistor(s) and having its output connected to the bootstrap terminals for providing a voltage to the region outside the transistor(s) which follows the voltage developed on the parasitic capacitance and nullifies the parasitic capacitance.

Abstract: A linear interpolation network for a continuously variable amplifier. The interpolation network includes first and second control terminals from which complementary scanning input currents are demanded. The network includes a plurality of circuit legs. Each leg includes a current source and a diode connect in series therewith. Coupled between each pair of adjacent circuit legs are first and second shunting diodes. The first shunting diode is connected between the adjacent legs to conduct current in a first direction. The second shunting diode is connected between the adjacent legs to conduct current is a second, opposite direction. The shunting diodes shunt current from the current sources to the control terminals to meet the current demands of the complementary scanning current input signals. The remaining current is sourced by one or more legs such that substantially triangular, overlapping current pulses are produced in the legs responsive to the scanning current inputs.

Abstract: A process for fabricating an IGFET integrated circuit having two gate dielectric layers with different parameters is provided. Typically, the process is used for fabrication of dual voltage CMOS integrated circuits. The integrated circuit may include high voltage transistors having a first gate dielectric thickness and low voltage transistors having a second gate dielectric thickness. A first gate dielectric layer and a first gate layer for the high voltage transistors are formed over active regions of a substrate. The device is patterned to expose low voltage transistor areas, and the first gate dielectric layer and the first gate layer are removed in the low voltage transistor areas. Then, a second gate dielectric layer and a second gate layer for the low voltage transistors are formed on the device. The device is patterned to expose the high voltage transistor areas, and the second gate dielectric layer and the second gate layer are removed in the high voltage transistor areas.

Abstract: A precision switched capacitor ratio system includes a capacitor; a switching device for selectively interconnecting the capacitor with one of a plurality of charging circuits and alternately connecting it with a discharge circuit for discharging the capacitor between each interconnection with a charging current; an integrating device interconnected with the capacitor for averaging the current during the charging and discharging of the capacitor for defining the switched capacitor equivalent resistance; and a clock device for providing synchronized clock signals for operating the switching device to precisely define the ratio of the frequencies of the interconnection of the capacitor with each of the charging circuits.

Abstract: A circuit for varying the temperature of a first bipolar transistor in order to thermally compensate for self-heating effects of an associated device in a common signal path with the first transistor, the first transistor being configured within an isolated collector region. The circuit includes a second bipolar transistor provided within the isolated collector region and thermally coupled to the first transistor, the second transistor operable for providing heat to the first transistor to alter the temperature to a predetermined level, thus changing the operational voltage characteristics of the first transistor so as to minimize shifts in offset voltage.

Abstract: A low distortion CMOS switch system includes a plurality of N-channel and a plurality of P-channel transistors with their drain and source terminals connected in parallel for receiving an input signal to be switched; and a control circuit for providing a different positive drive voltage to the gate of each of the N-channel transistors and a different negative drive voltage to the gate of each of the P-channel transistors to produce substantially constant "on" resistance, R.sub.ON, throughout the range of the switched signal conducted through the drain and source terminals, and for providing the same negative drive voltage to the gate of each of the N channel transistors and the same positive drive voltage to the gate of each of the P channel transistors to turn off the transistors.

Abstract: A hybrid analog/digital automatic gain control gain recovery system includes a variable gain amplifier (VGA) for receiving a variable amplitude input signal; a first AGC loop includes an analog to digital converter (DAC) for receiving the analog input signal and converting it to a digital signal; a digital gain error detection circuit for detecting variations of the digital signal in a first range and generating a digital error correction signal; and a digital to analog converter (DAC) for converting the digital error correction signal to a first analog correction signal; a second analog AGC loop includes an analog gain error detection circuit, responsive to variations in the output of the VGA in a second range greater than the first range for generating a second analog correction signal; and an integrator circuit responsive to the first and second analog correction signals for providing to the VGA a control signal to adjust the gain of the VGA to accommodate variations in the input signal amplitude.

Abstract: An improved back gate switched sample and hold circuit includes a sample and hold channel including a sample switch having a back gate and a storage element; a back gate circuit for controlling the back gate of the sample switch; and a first attenuator circuit for scaling the input signal from a low impedance source for delivery to the sample switch and a second attenuator circuit responsive to the input signal from the low impedance source to independently drive the back gate circuit and isolate any distortion of the input signal in the back gate circuit from affecting the input signal in said sample and hold channel.

Abstract: An MOS transistor wherein the channel between the source and drain is formed with two regions having different dopant concentrations. The region adjacent the source has a normal concentration, while that adjacent the drain has a reduced dopant concentration. This reduces the degrading effects of hot carrier injection, thereby extending the life of the transistor.

Abstract: A double-folded cascode operational amplifier capable of operating with rail-to-rail common mode inputs includes two differential input transistor pairs of opposite conductivity, with an associated current source and input resistor pair for each pair of input transistors. Its gain stage includes two interconnected pairs of folded cascode gain transistors that are connected to the two pairs of input resistors so that a change in the differential input signal produces a corresponding change in the gain stage output via the resistors. An output stage includes transistor-resistor circuitry to bias a pair of output transistors in opposite directions and produce a net amplifier output at their junction.

Abstract: The invention is a monolithic sensor comprising a silicon substrate, a suspended polysilicon microstructure for sensing a condition disposed above and suspended from the substrate, and circuitry for resolving a signal based on said sensed condition, the circuitry including bipolar circuit elements and MOS circuit elements. One disclosed embodiment is particularly adapted for sensing acceleration by means of a differential capacitor arrangement in which one capacitor plate in the arrangement is moveable responsive to an acceleration.

Abstract: An operational amplifier input circuit for preventing phase reversal and maintaining performance for inputs outside the common mode range includes a pair of differentially connected transistors for receiving respective differential inputs, and a folded cascode pair of transistors that are coupled to the differential transistors. A pair of resistors are connected between a reference potential and the current circuits of the differential and cascode transistors to produce resistor voltages that control the respective cascode transistors' currents. The differential transistors respond to an input by producing a forward biased parasitic diode in one of the differential transistors. A phase compensation circuit responds to the input by shifting the resistor voltage for the other differential transistor to prevent a phase reversal of the resistor voltages.

Abstract: Low jitter ring oscillators are disclosed. The oscillators obtain their low jitter through the use of gates (100) and interpolators (160) having time delays of superior stability. The stability is obtained with decoupling networks (140) and delay replica generators (222) that isolate power supply noise from critical circuit parameters.

Abstract: An integrated circuit including a semiconductor substrate, a semiconductor layer formed on the substrate, a desired bipolar transistor formed in the semiconductor layer. First and second parasitic elements are formed in the integrated circuit. An element is provided which detects when the second parasitic element becomes active or which prevents increase of the collector-to-emitter voltage of the desired bipolar transistor in response to current flowing through the second parasitic transistor. This element may be a semiconductor region formed in the semiconductor layer. The transistor may be an npn or pnp type transistor manufactured according to a complementary bipolar process or other process which results in a transistor with first and second parasitic elements. The present invention is also well-suited for use in the output stage of an operational amplifier.

Abstract: A sample-and-hold amplifier in which the held signal is represented as a voltage across a capacitor, but all other signals are represented as currents. At a summing node, the input current and a feedback current are summed to produce a difference current. In the tracking mode, this difference current flows through a closed hold switch onto the input of an integrator. The integrator accumulates the difference current onto the hold capacitor, where it becomes the hold voltage. This hold voltage is converted into a feedback current by a first transconductance amplifier, to provide the negative feedback to the summing node. The hold voltage, which need not equal the input signal, is also applied to the input of a second transconductance amplifier, which provides an output current. The ratio of the two transconductance gains determines the gain accuracy and linearity of the current output.

Abstract: An improved charge pump circuit includes a charge pump capacitor having first and second terminals for charging in first and second polarities; a current source device for supplying current selectively to the charge pump capacitor through the first and second terminals; a clamping device for defining first and second clamping voltages for the first and second terminals, respectively; a switching device for selectively connecting the current source device to one of the terminals and connecting the clamping device to the other of the terminals; and a clamp control device, responsive to the differential mode voltage across the charge pump capacitor, for setting the clamping voltages to obtain a difference between the clamping voltages equal to said differential mode voltage and pumping equal charge into the charge pump capacitor in either polarity.

Abstract: A center frequency controlled phase locked loop system includes a primary phase locked loop having a first voltage controlled oscillator including a first voltage to current converter whose output current drives a first current controlled oscillator to produce the primary clock signal to be locked onto an input signal; a second phase locked loop having a second voltage controlled oscillator including a second voltage to current converter whose output current drives a second current controlled oscillator to produce the synthesized clock signal whose frequency is approximately that of the input signal or integral multiple thereof; and a current copier circuit for copying the output current from the second voltage to current converter and delivering it to the first current controlled oscillator to maintain the center frequency of the first voltage controlled oscillator at approximately the output frequency of the synthesized clock signal.