Patents Assigned to Applied Material
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Patent number: 11488811Abstract: The present disclosure relates to methods and systems for chucking in substrate processing chambers. In one implementation, a method of chucking one or more substrates in a substrate processing chamber includes applying a chucking voltage to a pedestal. A substrate is disposed on a support surface of the pedestal. The method also includes ramping the chucking voltage from the applied voltage, detecting an impedance shift while ramping the chucking voltage, determining a corresponding chucking voltage at which the impedance shift occurs, and determining a refined chucking voltage based on the impedance shift and the corresponding chucking voltage.Type: GrantFiled: February 27, 2020Date of Patent: November 1, 2022Assignee: Applied Materials, Inc.Inventors: Bhaskar Kumar, Ganesh Balasubramanian, Vivek Bharat Shah, Jiheng Zhao
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Patent number: 11488812Abstract: In-situ low pressure chamber cleans and gas nozzle apparatus for plasma processing systems employing in-situ deposited chamber coatings. Certain chamber clean embodiments for conductor etch applications include an NF3-based plasma clean performed at pressures below 30 mT to remove in-situ deposited SiOx coatings from interior surfaces of a gas nozzle hole. Embodiments include a gas nozzle with bottom holes dimensioned sufficiently small to reduce or prevent the in-situ deposited chamber coatings from building up a SiOx deposits on interior surfaces of a nozzle hole.Type: GrantFiled: June 11, 2019Date of Patent: November 1, 2022Assignee: Applied Materials, Inc.Inventors: Xikun Wang, Andrew Nguyen, Changhun Lee, Xiaoming He, Meihua Shen
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Patent number: 11488835Abstract: Exemplary etching methods may include flowing a halogen-containing precursor into a remote plasma region of a semiconductor processing chamber while striking a plasma to produce plasma effluents. The methods may include contacting a substrate housed in a processing region with the plasma effluents. The substrate may define an exposed region of tungsten oxide. The contacting may produce a tungsten oxy-fluoride material. The methods may include flowing an etchant precursor into the processing region. The methods may include contacting the tungsten oxy-fluoride material with the etchant precursor. The methods may include removing the tungsten oxy-fluoride material.Type: GrantFiled: November 20, 2020Date of Patent: November 1, 2022Assignee: Applied Materials, Inc.Inventors: Zhenjiang Cui, Rohan Puligoru Reddy, Anchuan Wang
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Patent number: 11488830Abstract: Methods of depositing platinum group metal films of high purity, low resistivity, and good conformality are described. A platinum group metal film is formed in the absence of an oxidant. The platinum group metal film is selectively deposited on a conductive substrate at a temperature less than 200° C. by using an organic platinum group metal precursor.Type: GrantFiled: August 23, 2019Date of Patent: November 1, 2022Assignee: Applied Materials, Inc.Inventors: Yixiong Yang, Wei V. Tang, Seshadri Ganguli, Sang Ho Yu, Feng Q. Liu, Jeffrey W. Anthis, David Thompson, Jacqueline S. Wrench, Naomi Yoshida
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Patent number: 11487304Abstract: A method includes identifying time values for a length of time to carry out process fluid delivery within multiple processing chambers that concurrently process multiple substrates; translating each time value to a recipe parameter for execution of an operation of a processing recipe; and causing the operation to be performed using each recipe parameter as a control value to control valves of a fluid panel of the multiple processing chambers. For each processing chamber of the multiple processing chambers: causing the process fluid to flow to the processing chamber for a first period of time corresponding to a first time value; and causing the process fluid to flow to a divert foreline of the processing chamber for a second period of time, the second period of time being based on a timestep of the operation and the time value.Type: GrantFiled: January 8, 2021Date of Patent: November 1, 2022Assignee: Applied Materials, Inc.Inventors: Mitesh Sanghvi, Venkatanarayana Shankaramurthy, Peter Standish, Anton Baryshnikov, Thorsten Kril, Chahal Neema, Vishal Suresh Jamakhandi, Abhijit Ashok Kangude
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Patent number: 11488935Abstract: A network-on-package (NoPK) for connecting a plurality of chiplets may include a plurality of interface bridges configured to convert a plurality of protocols used by the plurality of chiplets into a common protocol, a routing network configured to route traffic between the plurality of interface bridges using the common protocol, and a controller configured to program the plurality of interface bridges and the routing network based on types of the plurality of chiplets connected to the NoPK. The NoPK may provide a scalable connection for any number of chiplets from different ecosystems using different communication protocols.Type: GrantFiled: May 7, 2021Date of Patent: November 1, 2022Assignee: Applied Materials, Inc.Inventors: Naveed Zaman, Myron Shak, Tameesh Suri, Bilal Shafi Sheikh
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Patent number: 11488796Abstract: Embodiments disclosed herein include a high-frequency emission module. In an embodiment, the high-frequency emission module comprises a solid state high-frequency power source, an applicator for propagating high-frequency electromagnetic radiation from the power source, and a thermal break coupled between the power source and the applicator. In an embodiment, the thermal break comprises a substrate, a trace on the substrate, and a ground plane.Type: GrantFiled: March 24, 2020Date of Patent: November 1, 2022Assignee: Applied Materials, Inc.Inventors: Thai Cheng Chua, Hanh Nguyen, Philip Allan Kraus
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Patent number: 11487139Abstract: Embodiments of metasurfaces having nanostructures with desired geometric profiles and configurations are provided in the present disclosure. In one embodiment, a metasurface includes a nanostructure formed on a substrate, wherein the nanostructure is cuboidal or cylindrical in shape. In another embodiment, a metasurface includes a plurality of nanostructures on a substrate, wherein each of the nanostructures has a gap greater than 35 nm spaced apart from each other. In yet another embodiment, a metasurface includes a plurality of nanostructures on a substrate, wherein the nanostructures are fabricated from at least one of TiO2, silicon nitride, or amorphous silicon, or GaN or aluminum zinc oxide or any material with refractive index greater than 1.8, and absorption coefficient smaller than 0.001, the substrate is transparent with absorption coefficient smaller than 0.001.Type: GrantFiled: October 14, 2019Date of Patent: November 1, 2022Assignee: Applied Materials, Inc.Inventors: Tapashree Roy, Wayne McMillan, Rutger Meyer Timmerman Thijssen
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Patent number: 11487848Abstract: The subject matter of this specification can be implemented in, among other things, a method, system, and/or device to receive current metrology data for an operation on a current sample in a fabrication process. The metrology data includes a current value for a parameter at each of one or more locations on the current sample. The method includes obtaining a reference rate of change of the parameter value of the parameter for each of the one or more locations. The method further includes determining a current rate of change of the parameter value for each of the one or more locations. The current rate of change is associated with the current sample. The method further includes comparing the current rate of change of the parameter value to the reference rate of change of the parameter value and identifying an instance of abnormality of the fabrication process based on the comparison.Type: GrantFiled: January 29, 2021Date of Patent: November 1, 2022Assignee: Applied Materials, Inc.Inventors: Selim Nahas, Joseph James Dox, Vishali Ragam, Eric J. Warren, Shijing Wang, Charles Largo, Christopher Reeves, Randy Raynaldo Corral
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Publication number: 20220344275Abstract: Electronic devices and methods of forming electronic devices using a ruthenium or doped ruthenium liner and cap layer are described. A liner with a ruthenium layer and a cobalt layer is formed on a barrier layer. A conductive fill forms a second conductive line in contact with the first conductive line.Type: ApplicationFiled: July 6, 2022Publication date: October 27, 2022Applicant: Applied Materials, Inc.Inventors: Wenjing Xu, Feng Chen, Tae Hong Ha, Xianmin Tang, Lu Chen, Zhiyuan Wu
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Publication number: 20220344172Abstract: Exemplary etching methods may include flowing an oxygen-containing precursor into a processing region of a semiconductor processing chamber. The methods may include contacting a substrate housed in the processing region with the oxygen-containing precursor. The substrate may include an exposed region of ruthenium, and the contacting may produce ruthenium tetroxide. The methods may include vaporizing the ruthenium tetroxide from a surface of the exposed region of ruthenium. An amount of oxidized ruthenium may remain. The methods may include contacting the oxidized ruthenium with a hydrogen-containing precursor. The methods may include removing the oxidized ruthenium.Type: ApplicationFiled: April 26, 2021Publication date: October 27, 2022Applicant: Applied Materials, Inc.Inventors: Baiwei Wang, Xiaolin C. Chen, Rohan Puligoru Reddy, Oliver Jan, Zhenjiang Cui, Anchuan Wang
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Publication number: 20220344134Abstract: Methods and apparatus for processing substrates are provided herein. In some embodiments, a process kit for a substrate support includes: an upper edge ring made of quartz and having an upper surface and a lower surface, wherein the upper surface is substantially planar and the lower surface includes a stepped lower surface to define a radially outermost portion and a radially innermost portion of the upper edge ring.Type: ApplicationFiled: July 11, 2022Publication date: October 27, 2022Applicant: Applied Materials, Inc.Inventors: Muhannad MUSTAFA, Muhammad M. RASHEED, Yu LEI, Avgerinos V. GELATOS, Vikash BANTHIA, Victor H. CALDERON, Shi Wei TOH, Yung-Hsin LEE, Anindita SEN
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Publication number: 20220341034Abstract: Exemplary deposition methods may include delivering a boron-containing precursor to a processing region of a semiconductor processing chamber. The methods may include delivering a dopant-containing precursor with the boron-containing precursor. The dopant-containing precursor may include a metal. The methods may include forming a plasma of all precursors within the processing region of the semiconductor processing chamber. The methods may include depositing a doped-boron material on a substrate disposed within the processing region of the semiconductor processing chamber. The doped-boron material may include greater than or about 80 at. % of boron in the doped-boron material.Type: ApplicationFiled: April 26, 2021Publication date: October 27, 2022Applicant: Applied Materials, Inc.Inventors: Aykut Aydin, Rui Cheng, Karthik Janakiraman
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Publication number: 20220344171Abstract: Embodiments herein are directed to localized stress modulation by implanting a first side of a substrate to reduce in-plane distortion along a second side of the substrate. In some embodiments, a method may include providing a substrate, the substrate comprising a first main side opposite a second main side, wherein a plurality of features are disposed on the first main side, performing a metrology scan to the first main side to determine an amount of distortion to the substrate due to the formation of the plurality of features, and depositing a stress compensation film along the second main side of the substrate, wherein a stress and a thickness of the stress compensation film is determined based on the amount of distortion to the substrate. The method may further include directing ions to the stress compensation film in an ion implant procedure.Type: ApplicationFiled: August 6, 2021Publication date: October 27, 2022Applicant: Applied Materials, Inc.Inventors: Sony Varghese, Pradeep Subrahmanyan, Dennis Rodier, Kyuha Shim
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Publication number: 20220344453Abstract: Methods may include providing a device structure including a well formed in an epitaxial layer, and forming a plurality of shielding layers in the device structure, wherein at least one shielding layer is formed between a pair of adjacent sacrificial gates of a plurality of sacrificial gates. The method may further include forming a contact over the at least one shielding layer, forming a fill layer over the contact, and forming a plurality of trenches into the device structure, wherein at least one trench of the plurality of trenches is formed between a pair of adjacent shielding layers of the plurality of shielding layers, and wherein the at least one trench of the plurality of trenches is defined in part by a sidewall of the fill layer. The method may further include forming a gate structure within the at least one trench of the plurality of trenches.Type: ApplicationFiled: April 23, 2021Publication date: October 27, 2022Applicant: Applied Materials, Inc.Inventors: Qintao Zhang, Samphy Hong, Jason Appell, David J. Lee
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Publication number: 20220344282Abstract: Provided are methods of reducing the stress of a semiconductor wafer. A wafer map of a free-standing wafer is created using metrology tools. The wafer map is then converted into a power spectral density (PSD) using a spatial frequency scale. The fundamental component of bow is then compensated with a uniform film, e.g., silicon nitride (SiN), deposited on the back side of the wafer.Type: ApplicationFiled: April 27, 2022Publication date: October 27, 2022Applicant: Applied Materials, Inc.Inventors: Pradeep K. Subrahmanyan, Sean S. Kang, Sony Varghese
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Publication number: 20220343960Abstract: A sense amplifier reference is generated with the same memory cell columns as data cells in order to match signal paths between the data and reference signals. Each row of data memory cells may have a corresponding set of reference cells, which greatly reduces the number of data cells supported by a reference, and in turn reduces the impact of process variations. A memory array may include data columns, a first reference column in the memory array configured to provide a logic 0 reference signal, and a second reference column in the memory array configured to provide a logic 1 reference signal. A circuit is configured to combine at least the logic 0 reference signal and the logic 1 reference signal to generate a reference signal for a sense amplifier to identify the data signal provided from the data columns.Type: ApplicationFiled: April 23, 2021Publication date: October 27, 2022Applicant: Applied Materials, Inc.Inventor: Frank Tzen-Wen Guo
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Publication number: 20220341029Abstract: Apparatus and methods for controlling plasma profiles during PVD deposition processes are disclosed. Some embodiments utilize EM coils placed above the target to control the plasma profile during deposition.Type: ApplicationFiled: July 11, 2022Publication date: October 27, 2022Applicant: Applied Materials, Inc.Inventors: Alexander Jansen, Keith A. Miller, Prashanth Kothnur, Martin Riker, David Gunther, Emily Schooley
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Publication number: 20220343975Abstract: Methods and architectures for refreshing memory elements in a memory array may initialize a reference array that stores each of the possible values stored in the memory element. The values in the memory array and the reference array will drift in parallel over time. To perform a refresh, the drifted values may be read from the reference array and mapped to the original values that were stored when the reference array was initialized. Next, each value may be read from the memory array and matched with a corresponding value from the reference array. The known original value stored in the reference array can then be used to refresh the corresponding memory element in the memory array.Type: ApplicationFiled: April 23, 2021Publication date: October 27, 2022Applicant: Applied Materials, Inc.Inventor: Christophe J. Chevallier
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Patent number: 11479855Abstract: Apparatus and methods to process one or more wafers are described. A processing chamber comprises a first processing station comprising a first gas injector having a first face, a first emissivity and a first temperature, a second processing station comprising a second gas injector having a second face, a second emissivity and a second temperature, and a substrate support assembly comprising a plurality of substantially coplanar support surfaces, the substrate support assembly configured to move the support surfaces between the first processing station and the second processing station. When a wafer is on the support surfaces, a temperature skew of less than about 0.5° C. is developed upon moving the wafer between the stations in about 0.5 seconds.Type: GrantFiled: August 25, 2020Date of Patent: October 25, 2022Assignee: Applied Materials, Inc.Inventors: Joseph AuBuchon, Sanjeev Baluja, Dhritiman Subha Kashyap, Jared Ahmad Lee, Tejas Ulavi, Michael Rice
