Abstract: Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers include a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.

Abstract: Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with increased cell density. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells. Some embodiments form 3D NAND devices with smaller CD memory holes. Some embodiments form 3D NAND devices with silicon layer between alternating oxide and nitride materials.

Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a plasma etch apparatus includes a plasma etch chamber. The plasma etch chamber includes a plasma source disposed in an upper region of the plasma etch chamber, a cathode assembly disposed below the plasma source, and a support pedestal for supporting a substrate carrier below the plasma source. The plasma etch apparatus also includes a transfer chamber coupled to the plasma etch chamber. The transfer chamber includes a transfer arm for supporting a substantial portion of a dicing tape of the substrate carrier, the transfer arm configured to transfer a sample from the support pedestal following an etch singulation process.

Abstract: An apparatus for positioning micro-devices on a substrate includes one or more supports to hold a donor substrate and a destination substrate, an adhesive dispenser to deliver adhesive on micro-devices on the donor substrate, a transfer device including a transfer surface to transfer the micro-devices from the donor substrate to the destination substrate, and a controller. The controller is configured to operate the adhesive dispenser to selectively dispense the adhesive onto selected micro-devices on the donor substrate based on a desired spacing of the selected micro-devices on the destination substrate. The controller is configured to operate the transfer device such that the transfer surface engages the adhesive on the donor substrate to cause the selected micro-devices to adhere to the transfer surface and the transfer surface then transfers the selected micro-devices from the donor substrate to the destination substrate.

Abstract: An apparatus for processing a flexible substrate is provided including a vacuum chamber having a first chamber portion, second chamber portion and third chamber portion. The apparatus further includes an unwinding shaft supporting the flexible substrate to be processed and a winding shaft supporting the flexible substrate after processing, wherein the unwinding shaft and the winding shaft are disposed in the first chamber portion, a first wall separating the first chamber portion from the second chamber portion, wherein the first wall is inclined with respect to a vertical and horizontal orientation, a coating drum having a first portion disposed in the second chamber portion and a second portion disposed in the third chamber portion, and a plurality of processing stations disposed at least partially in the third chamber portion, wherein a majority of the plurality of the processing stations are disposed below a rotational axis of the coating drum.

Abstract: The present disclosure is a method of bonding an electrostatic chuck to a temperature control base. According to the embodiments, a bonding layer is formed between a dielectric body comprising the electrostatic chuck and a temperature control base. A flow aperture extends through the dielectric body and is aligned with a flow aperture in the temperature control base. The bonding layer is also configured with an opening that aligns with apertures in the dielectric body and the temperature control base. In one aspect, a porous plug may be disposed within the flow aperture to protect the bonding layer. In another aspect, a seal is disposed within the flow aperture to seal off the boding layer from gases in the flow aperture.

Abstract: Disclosed are methods of forming a semiconductor device, such as a finFET device. One non-limiting method may include providing a semiconductor device including a substrate and a plurality of fins extending from the substrate, and forming a source trench isolation (STI) material over the semiconductor device. The method may further include recessing the STI material to reveal an upper portion of the plurality of fins, implanting the semiconductor device, and forming a capping layer over the plurality of fins and the STI material. The method may further include removing a first fin section of the plurality of fins and a first portion of the capping layer, wherein a second fin section of the plurality of fins remains following removal of the first fin section.

Abstract: An EUV lithography system and method of manufacturing thereof includes: an EUV light source; a chuck being thermally conducting and smooth having a surface with a predetermined chuck flatness; and a reflective lens system for directing EUV light from the EUV light source over the surface of the chuck.

Abstract: Methods of producing gratings with trenches having variable height and width are provided. In one example, a method includes providing an optical grating layer atop a substrate, and providing a patterned hardmask over the optical grating layer. The method may include forming a mask over just a portion of the optical grating layer and the patterned hardmask, and etching a plurality of trenches into the optical grating layer to form an optical grating. After trench formation, at least one of the following grating characteristics varies between one or more trenches of the plurality of trenches: a trench depth and a trench width.

Abstract: Generally, embodiments described herein relate to methods for manufacturing an interconnect structure for semiconductor devices, such as in a dual subtractive etch process. An embodiment is a method for semiconductor processing. A titanium nitride layer is formed over a substrate. A hardmask layer is formed over the titanium nitride layer. The hardmask layer is patterned into a pattern. The pattern is transferred to the titanium nitride layer, where the transferring comprises etching the titanium nitride layer. After transferring the pattern to the titanium nitride layer, the hardmask layer is removed, where the removal comprises performing an oxygen-containing ash process.

Abstract: Embodiments herein provide systems and methods for multi-area selecting etching. In some embodiments, a system may include a plasma source delivering a plurality of angled ion beams to a substrate, the substrate including a plurality of devices. Each of the plurality of devices may include a first angled grating and a second angled grating. The system may further include a plurality of blocking masks positionable between the plasma source and the substrate. A first blocking mask of the plurality of blocking masks may include a first set of openings permitting the angled ion beams to pass therethrough to form the first angled gratings of each of the plurality of devices. A second blocking mask of the plurality of blocking masks may include a second set of openings permitting the angled ion beams to pass therethrough to form the second angled gratings of each of the plurality of devices.

Abstract: Embodiments of the disclosure generally relate to methods of forming gratings. The method includes depositing a resist material on a grating material disposed over a substrate, patterning the resist material into a resist layer, projecting a first ion beam to the first device area to form a first plurality of gratings, and projecting a second ion beam to the second device area to form a second plurality of gratings. Using a patterned resist layer allows for projecting an ion beam over a large area, which is often easier than focusing the ion beam in a specific area.

Abstract: A microwave antenna includes a first spiral conduit having a first conduit end, first plural ports in a floor of the first spiral conduit spaced apart along the length of the first spiral conduit; an axial conduit coupled to a rotatable stage; and a distributor waveguide comprising an input coupled to the axial conduit and a first output coupled to the first conduit end.

Abstract: Exemplary methods of etching semiconductor substrates may include flowing a halogen-containing precursor into a processing region of a semiconductor processing chamber. The processing region may house a substrate having a conductive material and an overlying mask material. The conductive material may be characterized by a first surface in contact with the mask material, and the mask material may define an edge region of the conductive material. The methods may include contacting the edge region of the conductive material with the halogen-containing precursor and the oxygen-containing precursor. The methods may include etching in a first etching operation the edge region of the conductive material to a partial depth through the conductive material to produce a footing of conductive material protruding along the edge region of the conductive material. The methods may also include removing the footing of conductive material in a second etching operation.

Abstract: Disclosed are methods of forming a semiconductor device, such as a finFET device. One non-limiting method may include providing a semiconductor device including a substrate and a plurality of fins extending from the substrate, and forming a source trench isolation (STI) material over the semiconductor device. The method may further include performing a fin cut by removing a first fin section of the plurality of fins and a first portion of the STI material, and forming a second STI material over a second fin section of the plurality of fins, wherein the second fin section is left remaining following removal of the first fin section. The method may further include recessing the STI material and the second STI material, forming a spin-on-carbon (SOC) layer over the semiconductor device, and implanting the STI material and the second STI material through the SOC layer.

Abstract: Mass flow verification systems and apparatus may verify mass flow rates of mass flow controllers (MFCs) based on choked flow principles. These systems and apparatus may include a plurality of differently-sized flow restrictors coupled in parallel. A wide range of flow rates may be verified via selection of a flow path through one of the flow restrictors based on an MFC's set point. Mass flow rates may be determined via pressure and temperature measurements upstream of the flow restrictors under choked flow conditions. Methods of verifying a mass flow rate based on choked flow principles are also provided, as are other aspects.

Abstract: Susceptor assemblies comprising a susceptor base and a plurality of pie-shaped skins thereon are described. A pie anchor can be positioned in the center of the susceptor base to hold the pie-shaped skins in place during processing.

Abstract: Implementations of the present disclosure relate to systems and techniques for abating F-gases present in the effluent of semiconductor manufacturing processes. In one implementation, a water and oxygen delivery system for a plasma abatement system is provided. The water and oxygen delivery system comprises a housing that includes a floor and a plurality of sidewalls that define an enclosed region. The water and oxygen delivery system further comprises a cylindrical water tank positioned on the floor, wherein a longitudinal axis of the cylindrical water tank is parallel to a plane defined by the floor and a length of the water tank is 1.5 times or greater than the diameter of the cylindrical water tank. The water and oxygen delivery system further comprises a flow control system positioned within the housing above the cylindrical water tank.

Abstract: Physical vapor deposition target assemblies and methods of manufacturing such target assemblies are disclosed. An exemplary target assembly comprises a flow pattern including a plurality of arcs and bends fluidly connected to an inlet end and an outlet end.

Abstract: The present disclosure generally relates to apparatuses and methods that control RF amplitude of an edge ring. The apparatuses and methods include an electrode that is coupled to ground through a variable capacitor. The electrode may be ring-shaped and embedded in a substrate support including an electrostatic chuck. The electrode may be positioned beneath the perimeter of a substrate and/or the edge ring. As the plasma sheath drops adjacent the edge ring due to edge ring erosion, the capacitance of the variable capacitor is adjusted in order to affect the RF amplitude near the edge of the substrate. Adjustment of the RF amplitude via the electrode and variable capacitor results in adjustment of the plasma sheath near the substrate perimeter.