Abstract: Physical vapor deposition target assemblies and methods of manufacturing such target assemblies are disclosed. An exemplary target assembly comprises a flow pattern including a plurality of arcs and bends fluidly connected to an inlet end and an outlet end.

Abstract: Embodiments of the present disclosure relate to gas abatement apparatus and effluent management. The apparatus described herein include a high pressure process chamber and a containment chamber surrounding the process chamber. A high pressure fluid delivery module is in fluid communication with the high pressure process chamber and is configured to deliver a high pressure fluid to the process chamber. An effluent management module includes a muffler assembly to effluent pressure reduction and a plurality of scrubbers provide for treatment of effluent.

Abstract: Aspects of disclosure provide a method for attaching wiring connections to a component using both design and field measured data of the component to produce accurate wiring connections.

Abstract: Described herein is a method of depositing a plasma resistant ceramic coating onto a surface of a chamber component using a non-line-of-sight (NLOS) deposition process, such as atomic layer deposition (ALD) and chemical vapor deposition (CVD). The plasma resistant ceramic coating consists of an erbium containing oxide, an erbium containing oxy-fluoride, or an erbium containing fluoride. Also described are chamber components having a plasma resistant ceramic coating of an erbium containing oxide, an erbium containing oxy-fluoride, or an erbium containing fluoride.

Abstract: Exemplary semiconductor processing systems may include a processing chamber, and may include a remote plasma unit coupled with the processing chamber. Exemplary systems may also include a mixing manifold coupled between the remote plasma unit and the processing chamber. The mixing manifold may be characterized by a first end and a second end opposite the first end, and may be coupled with the processing chamber at the second end. The mixing manifold may define a central channel through the mixing manifold, and may define a port along an exterior of the mixing manifold. The port may be fluidly coupled with a first trench defined within the first end of the mixing manifold. The first trench may be characterized by an inner radius at a first inner sidewall and an outer radius, and the first trench may provide fluid access to the central channel through the first inner sidewall.

Abstract: An additive manufacturing system includes a platen having a top surface to support an object being manufactured, a feed material dispenser to deliver a plurality of successive layers of feed material over the platen, an energy source positioned above the platen to fuse at least a portion of an outermost layer of feed material, and a coolant fluid dispenser to deliver a coolant fluid onto the outermost layer of feed material after at least a portion of the outermost layer has been fused.

Abstract: Exemplary apparatuses for centering and/or leveling a pedestal of a processing chamber may include a mounting block having a central axis, a set of first gauges mounted on the mounting block, and a set of second gauges mounted on the mounting block. The set of second gauges may be mounted substantially perpendicular to the set of first gauges. The plurality of first gauges may be configured to obtain measurements indicative of a degree of parallelism between a gas distribution plate of the processing chamber and the pedestal. The plurality of second gauges may be configured to obtain measurements indicative of a degree of axial alignment of a ring member of the processing chamber and the pedestal. The exemplary apparatuses may be used for centering and/or leveling the pedestal under vacuum.

Abstract: Exemplary methods of etching semiconductor substrates may include flowing a fluorine-containing precursor into a processing region of a semiconductor processing chamber. The processing region may house a substrate having an exposed region of a first silicon-containing material and an exposed region of a second silicon-containing material. The second silicon-containing material may be exposed within a recessed feature defined by the substrate. The methods may include flowing a silicon-containing precursor into the processing region of the semiconductor processing chamber. The methods may include forming a plasma within the processing region of the semiconductor processing chamber to generate plasma effluents of the fluorine-containing precursor and the silicon-containing precursor. The methods may include contacting the substrate with the plasma effluents. The methods may include removing at least a portion of the second silicon-containing material.

Abstract: Methods of depositing a carbon film are discussed. Some embodiments selectively deposit a carbon film on a metal surface over a dielectric surface. Some embodiments form carbon pillars on metal surfaces selectively over dielectric surfaces. Some embodiments utilize carbon pillars in forming self-aligned vias.

Abstract: A method for recycling a substrate process component of a processing chamber is provided. In one example, the recycling process includes retrieving a reference dimension for the substrate process component. The substrate process component includes a side wall having a bottom surface, an outer surface, a pre-defined wall thickness between the bottom surface and the outer surface, and a residue layer. The reference dimension corresponds to the pre-defined wall thickness. The recycling process includes machining the substrate process component with a mechanical cutting tool. The machining includes securing the substrate process component to a work piece holder and passing the mechanical cutting tool across the outer surface in a machining operation controlled by a controller to remove the residue layer. The controller uses the reference dimension to control the machining operation so that the substrate process component has the reference dimension after removal of the residue layer.

Abstract: Embodiments include a method for processing thin substrates. Embodiments may include electrostatically bonding a substrate to a first electrostatic carrier (ESC), with a backside of the substrate is facing away from the first ESC. Thereafter, the substrate may be thinned to form a thinned substrate. The thinned substrate may then be transferred to a second ESC with a front side of the thinned substrate facing away from the second ESC. Embodiments may include cleaning the front side surface of the thinned substrate and transferring the thinned substrate to a third ESC. In an embodiment, a backside of the thinned substrate is facing away from the third ESC. Embodiments may also include processing the backside surface of the thinned substrate, and transferring the thinned substrate to a tape frame.

Abstract: An apparatus and method are provided. In one embodiment. an apparatus may include a main chamber, where the main chamber includes an electrode assembly. The electrode assembly may include a plurality of electrodes arranged between a chamber entrance and a chamber exit of the main chamber. The apparatus may include a beam tunnel, connected to the chamber entrance, configured to conduct an ion beam to the main chamber; and an electrostatic tuner, disposed in the beam tunnel, the electrostatic tuner comprising at least one tuner electrode, independently coupled to a tuner voltage assembly.

Abstract: Data indicative of alignment targets may be received. Each alignment target may be associated with a target location on an object. Locations of the object to be inspected may be identified. An alignment target from the alignment targets may be selected. Each of the locations may be within a determined distance from the selected alignment target. An indication may be provided to align the object relative to an examination tool for inspecting the locations within the determined distance from the selected alignment target.

Abstract: Techniques are disclosed for methods and apparatuses for reducing particle contamination formation in a high temperature processing chamber with a cooled gas feed block. The cooled gas feed has a body. The body has a main center portion having a top surface and a bottom surface. The body also has a flange extending outward from the bottom surface of the main center portion. A gas channel is disposed through the body. The gas channel has an inlet formed in the top surface of the main center portion and an outlet formed in the bottom surface of the main center portion. The body also has a center coolant channel. The center coolant channel has a first portion having an inlet formed in the top surface of the main center portion, and a second portion coupled to the first portion, the second portion having an outlet formed a sidewall of the flange.

Abstract: Methods of dicing semiconductor wafers are described. In an example, a method of dicing a wafer having a plurality of integrated circuits thereon involves dicing the wafer into a plurality of singulated dies disposed above a dicing tape. The method also involves forming a material layer over and between the plurality of singulated dies above the dicing tape. The method also includes expanding the dicing tape, wherein a plurality of particles is collected on the material layer during the expanding.

Abstract: A system for determining various parameters of an ion beam is disclosed. A test workpiece may be modified to incorporate a detection pattern. The detection pattern may be configured to measure the height of the ion beam, the uniformity of the ion beam, or the central angle of the ion beam. In certain embodiments, the amount of current striking the detection pattern may be measured using an optical emission spectrometer (OES) system. In other embodiments, a power supply used to bias the workpiece may be used to measure the amount of current striking the detection pattern. Alternative, the detection patterns may be incorporated into the workpiece holder.

Abstract: In one aspect, a valve assembly adapted to seal an opening in a chamber is disclosed. Valve assembly includes a housing being adapted for coupling to a chamber surface having the opening therein, the housing including a threshold portion positioned adjacent to the chamber opening, the threshold portion having one or more inlets adapted to supply gas to an interior region of the housing adjacent to the chamber opening; and a sealing surface adapted to selectively (1) seal the opening, and (2) retract from the opening so as not to obstruct substrate passage. Numerous other system aspects are provided, as are methods and computer program products in accordance with these and other aspects.

Abstract: Described are semiconductor devices and methods of making semiconductor devices with a barrier layer comprising cobalt and manganese nitride. Also described are semiconductor devices and methods of making same with a barrier layer comprising CoMn(N) and, optionally, an adhesion layer.

Abstract: Embodiments herein provide film stacks that include a buffer layer; a synthetic ferrimagnet (SyF) coupling layer; and a capping layer, wherein the capping layer comprises one or more layers, and wherein the capping layer, the buffer layer, the SyF coupling layer, or a combination thereof, is not fabricated from Ru.

Abstract: Aspects of disclosure provide a method for attaching wiring connections to a component using both design and field measured data of the component to produce accurate wiring connections.