Abstract: A plasma etch process for etching high aspect ratio openings in a dielectric film on a workpiece is carried out in a reactor having a ceiling electrode overlying the workpiece and an electrostatic chuck supporting the workpiece. The process includes injecting a first polymerizing etch process gas through a radially inward one of plural concentric gas injection zones in the ceiling electrode and injecting a second polymerizing etch process gas through a radially outward one of the plural concentric gas injection zones in the ceiling electrode, the compositions of the first and second process gases having first and second carbon-to-fluorine ratios that differ from one another.

Abstract: Gate electrode structures used in field effect transistors and integrated circuits and methods of manufacture are disclosed. Improved work function and threshold modulation are provided by the methods and structures.

Abstract: A method for measuring the concentration of the metal solution and reducing agent solution within the electroless plating solution is disclosed. Raman spectroscopy is used to measure the concentration of each solution within the electroless plating solution after they have been mixed together. By measuring the concentration of each solution prior to providing the solution to a plating cell, the concentration of the individual solutions can be adjusted so that the targeted concentration of each solution is achieved. Additionally, each solution can be individually analyzed using Raman spectroscopy prior to mixing with the other solutions. Based upon the Raman spectroscopy measurements of the individual solutions prior to mixing, the individual components that make up each solution can be adjusted prior to mixing so that the targeted component concentration can be achieved.

Abstract: A break-away mounting system for a continuous-motion, high-speed position conveyor system is disclosed. A support cradle may be suspended from a conveyor belt such that the support cradle maintains a fixed position and orientation relative to at least one point on the conveyor belt without inducing appreciable stress on the conveyor belt, the support cradle, or the coupling between the conveyor belt and the support cradle. The mount may include a leading rotatable bearing attached to the support cradle which may releasably engage a first key attached to the conveyor belt, the rotatable bearing adapted to accommodate rotational forces applied to the support cradle by the conveyor belt. The mount may also include a slide bearing attached to the support cradle which may releasably engage a second key attached to the conveyor belt, the slide bearing adapted to accommodate longitudinal forces applied to the support cradle by the conveyor belt.

Abstract: A method of fabricating multilayer interconnect structures on a semiconductor wafer begins by roughening the interior surface of a metal lid to a surface roughness in excess of SA 2000 with a reentrant surface profile, and installing the metal lid as the ceiling of a plasma clean reactor chamber having a wafer pedestal facing the interior surface of the ceiling.

Abstract: Embodiments of the invention generally provide a composition of silicon compounds and methods for using the silicon compounds to deposit a silicon-containing film. The processes employ introducing the silicon compound to a substrate surface and depositing a portion of the silicon compound, the silicon motif, as the silicon-containing film. The ligands are another portion of the silicon compound and are liberated as an in-situ etchant. The in-situ etchants supports the growth of selective silicon epitaxy. Silicon compounds include SiRX6, Si2RX6, Si2RX8, wherein X is independently hydrogen or halogen and R is carbon, silicon or germanium. Silicon compound also include compounds comprising three silicon atoms, fourth atom of carbon, silicon or germanium and atoms of hydrogen or halogen with at least one halogen, as well as, comprising four silicon atoms, fifth atom of carbon, silicon or germanium and atoms of hydrogen or halogen with at least one halogen.

Abstract: A method of forming a silicon oxide layer on a substrate. The method includes providing a substrate and forming a first silicon oxide layer overlying at least a portion of the substrate, the first silicon oxide layer including residual water, hydroxyl groups, and carbon species. The method further includes exposing the first silicon oxide layer to a plurality of silicon-containing species to form a plurality of amorphous silicon components being partially intermixed with the first silicon oxide layer. Additionally, the method includes annealing the first silicon oxide layer partially intermixed with the plurality of amorphous silicon components in an oxidative environment to form a second silicon oxide layer on the substrate. At least a portion of amorphous silicon components are oxidized to become part of the second silicon oxide layer and unreacted residual hydroxyl groups and carbon species in the second silicon oxide layer are substantially removed.

Abstract: A plasma etch process etches high aspect ratio openings in a dielectric film on a workpiece in a reactor having a ceiling electrode overlying the workpiece and an electrostatic chuck supporting the workpiece. The process includes injecting a polymerizing etch process gas through an annular zone of gas injection orifices in the ceiling electrode, and evacuating gas from the reactor through a pumping annulus surrounding an edge of the workpiece. The high aspect ratio openings are etched in the dielectric film with etch species derived from the etch process gas while depositing a polymer derived from the etch process gas onto the workpiece, by generating a plasma in the reactor by applying VHF source power and/or HF and/or LF bias power to the electrodes at the ceiling and/or the electrostatic chuck.

Abstract: An electrode assembly 12 for a PECVD (Plasma Enhanced Chemical Vapour Deposition) coating installation comprises a base plate 13, a separation plate 14 and an electrode plate 15. The electrode plate 15 includes frame members 16. Fixing elements 17 are provided for fixing the electrode plate 15 to the base plate 13. Furthermore, the electrode assembly 12 comprises a plurality of gas distribution elements 2 that distribute process gas to provide a homogeneous plasma P above the surface of a substrate 19. In this way a uniform coating can be deposited on the substrate 19. The gas distribution elements 2 are modules having a similar or identical construction. Therefore, they may be manufactured in particular machines and handled easily before being integrated in an electrode assembly according to the present invention.

Abstract: According to a first aspect, a first conveyor system is provided that is adapted to deliver substrate carriers within a semiconductor device manufacturing facility. The first conveyor system includes a ribbon that forms a closed loop along at least a portion of the semiconductor device manufacturing facility. The ribbon is adapted to (1) be flexible in a horizontal plane and rigid in a vertical plane; and (2) transport a plurality of substrate carriers within at least a portion of the semiconductor device manufacturing facility. Numerous other aspects are provided, as are systems, methods and computer program products in accordance with these and other aspects.

Abstract: A method, a system and a computer readable medium for three dimensional packaging with wafer-level bonding and chip-level repair. A first wafer is provided having a first plurality of chips. A second wafer is provided having a second plurality of chips. At least one chip is removed from the second wafer while retaining the relative alignment of the remaining chips in the second wafer. The first and second wafers are aligned and joined with wafer-to-wafer techniques. Where a bad chip having a relative physical position within the second wafer corresponding to a relative physical position within the first wafer of a good chip is removed, a good chip may be aligned and bonded to the first wafer using die-to-wafer techniques.

Abstract: An apparatus for providing a short return current path for RF current between a process chamber wall and a substrate support is provided. The RF grounding apparatus, which is RF grounded and is place above the substrate transfer port, establishes electrical contact with the substrate support only during substrate processing, such as deposition, to provide return current path for the RF current. One embodiment of the RF grounding apparatus comprises one or more low impedance flexible curtains, which are electrically connected to the grounded chamber wall, and to one or more low impedance blocks, which make contacts with the substrate support during substrate processing. Another embodiment of the RF grounding apparatus comprises a plurality of low impedance flexible straps, which are electrically connected to the grounded chamber wall, and to one or more low impedance blocks, which make contacts with the substrate support during substrate processing.

Abstract: A method for focusing a charged particle beam, the method includes: (a) altering a focal point of a charged particle beam according to a first focal pattern while scanning a first area of a sample and collecting a first set of detection signals; (b) altering a focal point of a charged particle bean according to a second focal pattern while scanning a second area that is ideally identical to the first area and collecting a second set of detection signals; and (c) processing the first and second set of detection signals to determine a focal characteristic; whereas the first focal pattern and the second focal pattern differ by the location of an optimal focal point.

Abstract: An apparatus and a method of controlling an electroless deposition process by directing electromagnetic radiation towards the surface of a substrate and detecting the change in intensity of the electromagnetic radiation at one or more wavelengths reflected off features on the surface of the substrate. In one embodiment the detected end of an electroless deposition process step is measured while the substrate is moved relative to the detection mechanism. In another embodiment multiple detection points are used to monitor the state of the deposition process across the surface of the substrate. In one embodiment the detection mechanism is immersed in the electroless deposition fluid on the substrate. In one embodiment a controller is used to monitor, store, and/or control the electroless deposition process by use of stored process values, comparison of data collected at different times, and various calculated time dependent data.

Abstract: A method and apparatus for testing a plurality of electronic devices formed on a large area substrate is described. In one embodiment, the apparatus performs a test on the substrate in one linear axis in at least one chamber that is slightly wider than a dimension of the substrate to be tested. Clean room space and process time is minimized due to the smaller dimensions and volume of the system.

Abstract: Methods are disclosed of fabricating a compound nitride semiconductor structure. A substrate is disposed over a susceptor in a processing chamber, with the susceptor in thermal communication with the substrate. A group-III precursor and a nitrogen precursor are flowed into the processing chamber. The susceptor is heated with a nonuniform temperature profile to heat the substrate. A nitride layer is deposited over the heated substrate with a thermal chemical vapor deposition process within the processing chamber using the group-III precursor and the nitrogen precursor.

Abstract: A substrate is maintained beneath a substrate mounting surface with a retaining ring that includes a generally annular lower portion having a bottom surface for contacting the polishing surface during polishing, and a generally annular upper portion having a bottom surface joined to the lower portion and a top surface fixed to and abutting the base. The lower portion is made of a plastic and the upper lower portion is made of a metal which is more rigid than the plastic.

Abstract: Substrate processing systems are described. The systems may include a processing chamber, and a substrate support assembly at least partially disposed within the chamber. The substrate support assembly is rotatable by a motor yet still allows electricity, cooling fluids, gases and vacuum to be transferred from a non-rotating source outside the processing chamber to the rotatable substrate support assembly inside the processing chamber. Cooling fluids and electrical connections can be used to raise or lower the temperature of a substrate supported by the substrate support assembly. Electrical connections can also be used to electrostatically chuck the wafer to the support assembly. A rotary seal or seals (which may be low friction O-rings) are used to maintain a process pressure while still allowing substrate assembly rotation. Vacuum pumps can be connected to ports which are used to chuck the wafer.

Abstract: An exhaust foreline for purging fluids from a semiconductor fabrication chamber is described. The foreline may include a first, second and third ports independently coupled to the chamber. A semiconductor fabrication system is also described that includes a substrate chamber that has a first, second and third interface port. The system may also include a multi-port foreline that has a first, second and third port, where the first foreline port is coupled to the first interface port, the second foreline port is coupled to the second interface port, and the third foreline port is coupled to the third interface port. The system may further include an exhaust vacuum coupled to the multi-port foreline.