Abstract: A method and apparatus includes processing for modifying memory accesses, which begins by receiving a memory transaction. The processing continues by determining whether a translation look-aside table (TLB) entry exists for the memory access transaction. If a TLB entry does not exist, one is generated. Once a TLB entry exists for the memory access transaction, a transaction tag within the TLB is interpreted to identify an exception or a memory address space from a plurality of memory address spaces. The processing continues by interpreting the TLB entry to obtain a physical address when the tag identifies the memory address space. Having obtained the physical address, the memory address transaction is processed utilizing the physical address within the corresponding memory address space.

Abstract: A method and apparatus for providing a three-dimensional object on live video includes processing that begins by filling at least a portion of a back butler with a key color, where the key color indicates the presentation of the video. The processing then continues by writing the three-dimensional object into the back buffer. Note that by providing the key color into the back buffer as a clearing operation or having a back most Z value, when the three-dimensional object is written into the back buffer, it will be in a foreground viewing perspective with respect to the live video. The processing then continues by flipping the back buffer to become a primary surface such that the data stored in the primary surface is subsequently displayed on a display device.

Abstract: The present invention provides an apparatus and a method for address generation. In one embodiment, an apparatus for an address generation unit of an ALU (Arithmetic Logic Unit) of a microprocessor includes a first carry-propagate adder that adds a lower 16 bits of a constant or displacement and a lower 16 bits of a segment base, and a second carry-propagate adder connected to the first carry-propagate adder, wherein the second carry-propagate adder adds a lower 16 bits of a base and an output of the first 16-bit carry-propagate adder to generate a lower 16 bits of an address. In one embodiment, the first carry-propagate adder and the second carry-propagate adder are each 16-bit carry-propagate adders.

Abstract: A method and apparatus for storing and displaying video image data in a video graphics system is accomplished by receiving a video data stream, where the video data stream includes compressed video image data. The video image stream is parsed to separate the compressed video image data from other data within the data stream. The compressed video image data is decompressed to produce video image data that includes a luminosity plane, a first color plane, and a second color plane. Members of the first and second color planes are compacted together to form color pairs where a plurality of the color pairs form a color line. Each of the color lines is interleaved with at least one luminosity line to produce an interleaved plane. The interleaved plane is stored in memory. Portions of the interleaved video image data are retrieved from the interleaved plane. The portions are structured such that video image data that are located near each other within the memory are fetched together.

Abstract: A method and apparatus for processing video signals to a plurality of video outputs may be done within a video system that includes a video decoder, a digital-to-analog module, and an output control module. In such a video system, the video decoder includes an analog-to-digital conversion module for converting an input video signal(s) into a digital video signal(s). The video decoder further includes a comb filter that is operably coupled to receive the digital video signal and to produce therefrom a Y component digital signal and a C component digital signal. The output control module is operably coupled to receive the Y and C component digital signals and also to receive an output command. If the output command dictates, the output control module provides the Y and C component digital signals to the digital-to-analog module. In response, the digital-to-analog module produces a composite video output and an S video output.

Abstract: A method and apparatus for encoding a stream of data blocks begins when a stream of data blocks is received. The stream of data blocks may include a plurality of sequences of data blocks. The encoding process then continues by storing a first grouping of data blocks of a first sequence in non-local memory. Having stored the first grouping in non-local memory, one of the data blocks is retrieved from the non-local memory. The retrieved data block is then encoded utilizing a working section of local memory based on a relational data encoding convention. Next, the encoding process retrieves a second data block of the first grouping of data blocks from the non-local memory. In addition, portions of the first data block will be retrieved from the non-local memory and provided to a reference section of local memory. The second data block is then encoded in a working section of local memory based on the portions of the first data block and the relational data encoding convention.

Abstract: A method and apparatus for address paging emulation includes processing that begins by producing an extended logical address in response to a memory access request. The extended logical address includes a logical address and an address extension. The processing then continues by determining whether an entry exists for the memory access request in a translation look aside table. Such a determination is based on the logical address. When an entry does not exists for the memory access request, the process continues by providing the extended logical address to a plurality of exception handlers. The exception handlers interpret the address extension to identify one of the exception handlers to process the extended logical address. The exception handlers include a page exception handler, a non-page exception handler, a native processor exception handler, and a page directory entry exception handler.

Abstract: A method and apparatus for restricting memory access includes processing that begins by monitoring memory access requests. When one of the memory access requests is requesting access to restricted memory, determining the mode of operation of the processor. Note that the mode of operation of the processor may be a system special operation (i.e., operations internal to the operation of the computing system that are beyond access of computing system users and programmers), non-system special operations, or a valid response to a restricted memory access request. When the mode of operation is non-system special and the memory access is requesting access to restricted memory, the memory access request is modified. The processing then continues by providing a response in accordance with the modified memory access request.

Abstract: A frame buffer is divided into tiles of, for example, 32 by 32 pixels. Triangles (and portions thereof) that are within a given tile are rasterized one triangle at a time into the tile location. This process repeats for each tile in the image frame. A sorting circuit generates control bits representing a vertical order of the vertices of a current triangle. A series of multiplexers vertically sorts the vertices bases on these control bits. A region calculation circuit generates region bits representing a location each of the vertices with respect to the current tile. A trivial discard of the triangle data occurs if the region bits indicate that the entire triangle lies outside of the tile. Subsequently, an initial rasterization starting point is estimated based on the region bits to lower the time needed for the rasterizer to find the first pixel of the current triangle to be assigned values.

Abstract: A graphics processing device includes a variable performance setup engine that processes vertexes of polygons to create surface coefficients, and a rasterizer that processes the surface coefficients to create pixel values corresponding to each pixel location within each polygon. The variable performance setup engine is structured so as to provide the surface attributes of each polygon within a time that is correlated to the size of the polygon. In this manner, the overall polygon processing rate will be substantially related to the size of the polygon. By providing a short processing time for small polygons, and a longer processing time for larger polygons, the image processing rate is shown to be less dependent upon the sizes of the polygons that comprise the image. The invention thereby provides for an overall image processing rate that is substantially independent of the complexity of the image being rendered.

Abstract: An anti-aliasing technique for sampling an image for display on a pixel based display is presented. The image, or set of objects forming an image, is sampled at a resolution higher than the pixel spatial resolution. The resultant multiple sampled values for each pixel are accumulated, and the accumulated value is used to determine an average pixel value that is used for the display of the pixel. To minimize memory requirements, the rendering plane is used to temporarily store a portion of the accumulated value for each pixel. To minimize processing, the multiple of samples per pixel is a power of 2, and the portion of the accumulated value that is stored in the rendering plane is the most significant bits (MSB) of the accumulated value. Because of the use of a power of 2 as the number of samples, the MSB of the accumulated value is equal to the average of the accumulated value, and therefore the need for an explicit computation of an average for each pixel is eliminated.

Abstract: A method and apparatus for addressing memory in a processing system that includes a cache structure and supports multiple data streams is presented. The cache structure may be an N-way (where N is a number) cache that includes multiple sets or may be a simple set associative cache. A portion of the cache is divided into a number of blocks where each of the blocks is used to store data associated with a particular stream. Thus, different streams utilize different portions of the cache structure. In order to support the division of the stream portion of the cache into multiple blocks, addresses corresponding to stream data operations are modified for use in addressing the cache.

Abstract: A graphics processing device includes a graphic and video blender having an input operative to receive graphics or video data obtained from a frame buffer containing multiple formats of data for display on at least one of an RGB monitor and a television monitor. The processing device has an output and is operative to assign pixel type flags to output pixels in a blended image. A signal scaler is operatively coupled to receive the blended image from the graphic and video blender. A coefficient multiplexor selects coefficients for the signal scaler from a plurality of sets of coefficients in response to the assigned pixel type flag.

Abstract: A method and apparatus for manipulating the display update rate of video signals to minimize the adverse visual effects caused by adding or deleting frames begins by determining a need value for manipulation of the display update rate. The need value corresponds to increasing drift between the display update rate and the refresh rate. As such, as the drift increases between the display update rate and the refresh rate, the need value increases correspondingly. Next, an appropriateness value for manipulation of the display update rate is determined based on image content. In essence, the appropriateness value is determining whether, if a frame addition or deletion were to occur, would it occur at a point that would produce minimal adverse visual effects. Based on a relationship between the need value and the appropriateness value, the display update rate is manipulated by adding or deleting a frame.

Abstract: A method and apparatus for performing filtering operations on video data using a limited amount of memory is accomplished by multiplying a first coefficient value and a first input value to produce a product. A random number is generated and added to the product to produce a dithered product. The dithered product is added to an accumulated value to produce a partial sum. A truncated version of the partial sum is stored in a buffer as the new accumulated value. The multiply and add operations are repeated for a number of coefficient values and input values such that the accumulated value includes contributions from a number of different input values. The resulting accumulated value is provided as an output.

Abstract: A method and apparatus for processing memory access requests having enhanced functionality includes processing that begins by receiving a memory access request. The process continues by determining whether the memory access request triggers an address caching process to be performed. If so, the address caching process is performed. While performing the address caching process, a determination is made as to whether the address caching processing triggers an exception process to be performed based upon a physical address derived from the address caching process. Such address space requiring further processing includes video graphics address space, restricted memory space, read-only memory space, non-cacheable data memory space, device emulation exceptions memory space, and memory exceptions. When the exception process is triggered during the address caching process, the exception process is performed and the results are cached in an address processing cache.

Abstract: A video display apparatus and method for displaying decoded video frames from an encoded video stream utilizes a display time difference determinator that detects a frame display time difference, on a per frame basis if desired, between a refresh rate based frame display time, and a video playback frame rate display time to generate frame display time difference data. This is done on a continuous basis to detect synchronization problems between video data that is to be displayed simultaneously with non-video data on a display device such as a progressive display screen. A pixel blender blends pixel data from an adjacent frame, such as an already reconstructed previous frame or next frame, to create a temporally adjusted frame based on the determined frame display time difference data.

Abstract: A graphics system is used with a display capable of displaying a frame of an image via a sequence of scan lines. The graphics system has a memory and an image generator. The image generator is connected to store the data associated with some of the scan lines of the frame in a region of the memory, and before all of the data is retrieved from the region, store other data associated with another scan line in the region. The graphics system also has a display interface that is connected to retrieve the data associated with some of the scan lines from the region and use the data to form some of the scan lines on the display. The display interface is also connected to use the other data to form the next scan line in the sequence after the other scan lines are formed.

Abstract: A method and apparatus for sequencing memory accesses in a video graphics system such that page faults are effectively hidden is accomplished by receiving a memory access request from one of a plurality of clients, where the plurality of clients includes both linear clients and tiled memory clients. The clients access data stored in a memory that includes at least two banks. Once the memory request has been received, it is evaluated based on other pending requests in order to determine the optimal ordering pattern for execution of the memory requests. The optimal ordering pattern typically includes sequencing alternating accesses between the two banks of the memory such that when a page fault is occurring in one bank of the memory, a memory access is occurring in the opposing bank. Once the ordering of the memory requests has been performed, the requests are executed.

Abstract: A method and apparatus for processing data of different sizes begins by processing first data to produce an n-bit resultant. Such processing may be performing an arithmetic function upon the data. In addition, second data is processed to produce an m-bit resultant. Such processing of the second data may also include performing an arithmetic function upon the second data. The processing then continues by mixing the n-bit resultant with the m-bit resultant to produce an m-bit mixed resultant. For example, the first data may be representative of RGB graphics data that is processed by a graphics core to produce an 8-bit resultant. The second data may be representative of video data that is processed by a video core to produce a 10-bit resultant. A mixer mixes the 8-bit graphics output with the 10-bit digital video output to produce a 10-bit mixed output. A digital-to-analog converter converts the 10-bit mixed output into an analog signal.