Abstract: A method and apparatus for detecting validity of video transmissions in accordance with one of a plurality of channel identification plans is be accomplished by first detecting selection of a channel, wherein the channel corresponds to a particular video transmission. The signal strength of the video transmission is then tested over a frequency range relating to the channel. When the signal strength of the video transmission at a particular frequency exceeds a threshold, a video tuner utilizes the frequency to detect the video transmission. Upon detecting the video transmission, the video tuner outputs a base band signal of the video transmission to a video decoder. The video decoder converts the base band signal into a digitized video, which is checked to determine whether it includes a synchronization signal. If the digitized video includes a synchronization signal, the video transmission is deemed to be valid, i.e., it is in accordance with one of the plurality of channel identification plans.

Abstract: An amorphous metal alloy strip is disclosed having a width greater than about one inch and a thickness less than about 0.003 inch, this alloy consists essentially of 77 to 80 atomic percent iron, 12 to 16 atomic percent boron and 5 to 10 atomic percent silicon with incidental impurities. The strip has a 60 cycle per second core loss of less than about 0.100 watts per pound at 12.6 kilogauss, saturation magnetization of at least 15 kilogauss, and a coercive force of less than about 0.04 oersteds. Such alloy is further characterized by increased castability and the strip produced therefrom exhibits at least singular ductility. A method of producing such optimum strip is also disclosed.

Abstract: A voltage supply discriminator circuit senses multiple logic voltage supply levels and produces a plurality of control signals to select either or both of an output buffer circuit and/or an input buffer circuit that is coupled to a pad or pin. The discriminator circuit utilizes an input/output ring voltage supply and a reference voltage, such as a core voltage supply, to determine the appropriate circuitry to be used for the I/O pad. The appropriate circuitry is then automatically activated.

Abstract: A technique increases the number of colors output by an active color display by providing an increased number of grey levels for each pixel component. An M×N matrix pattern of pixel components is generated having a ratio of pixel components at a particular color level to pixel components at a different color level to achieve a particular grey level, where M and N are greater or equal to two. The M×N matrix pattern is repeated for X frames, and at least one pixel component is at the particular color level in each frame. At the end of the Nth frame, the matrix pattern from frame zero is repeated.

Abstract: Access to memory is facilitated by a cache memory access system that includes individual buffers for storing and processing data access commands asynchronously, while also assuring data coherency and avoiding deadlock. Data access commands are placed in discrete buffers, in dependence upon their type: read and write to and from a client process, fill from memory, and flush to memory. To maintain data coherency, the read and write commands are processed substantially sequentially. To optimize memory access, fills are processed as soon as they are submitted, and flushes may be given lower priority than fills. To avoid deadlock, fills are generated so as to be independent of all other commands. The use of discrete buffers for cache memory access is particularly well suited to pipeline processes.

Abstract: A conveyorized electroplating device having an anode positioned proximate to a plurality of absorptive applicator assemblies that apply a plating solution to a substrate and a conveyor device that grips the substrate thereby isolating the electrical contact from the plating solution. The conveyorized electroplating device has a fluid bed assembly with a manifold and an anode, a conveyor device adjacent to the fluid bed assembly, and a plurality of absorptive applicator assemblies, wherein the plurality of absorptive applicator assemblies are adjacent and in close proximity to the anode and in fluid communication with the fluid bed assembly. The conveyor device isolates the electrical contacts from the plating solution and is able to handle various sizes and thicknesses of substrates.

Abstract: A method and apparatus for adaptive noise filtering within a video graphics circuit includes determining an average intensity for a kernel of a display area. The kernel includes a plurality of pixels arranged in a particular manner, for example a square, a rectangle, etc. Next, a variance for a pixel within the kernel is determined. Based on a relationship between the average intensity and the variance, a signal-to-noise factor is determined. The signal-to-noise factor includes a noise region, a signal region, and an edge region. The pixel within the kernel is then adaptively filtered based on the signal-to-noise factor, the average intensity, and intensity of the pixel.

Abstract: A method and apparatus include processing which allows a graphics controller to extend its memory by receiving a client address and determining which of a plurality of system bus interfaces (e.g., AGP, PCI, ISA) is enabled. When a first type of system bus interface is enabled (e.g., PCI, ISA), a first system bus table index is generated based on the client address. The first system bus table index is used to access a first system bus table to retrieve a physical address of memory. The processing continues by obtaining data from the memory, wherein the data is stored at the physical address.

Abstract: A method and apparatus for transitioning between a first type of display data and a second type of display data begins by mapping the first display data onto a plurality of object elements in accordance with a first alteration level. Note that the plurality of object-elements corresponds to a display area, which is a full-screen of a display device or a portion thereof. The process then continues then by successively altering Z values and/or physical coordinates of the plurality of object-elements.

Abstract: An adder tree is partitioned into two parts. One multiplexer provides a first bit group to the first part of the tree. A second multiplexer provides a second bit group to the second part of the tree. The two multiplexers provide the same bits groups to the respective parts in response to a first instruction, and provide different bit groups in response to a second instruction. Therefore, the first instruction allows for the single multiplication of the number represented by the first bit group by another number provided to collectively represented to both parts of the tree. The second instruction causes the multiplication of the first bit group by the third bit group in the first part of the adder tree, and causes another multiplication of the second bit group by the fourth bit group in the second part of the adder tree.

Abstract: A systolic video encoding system processes image data from a frame buffer at a core clock rate that is independent of the sample rate of the image data. The video encoder of this invention uses the core clock rate of the host image processing system to process image from the frame buffer at this core clock rate. The image data is pumped out of the frame buffer, processed by each of the processes of the video encoder when the data reaches each of the processes, and the encoded samples are stored in a raster sample buffer for subsequent processing. The image data is continually pumped out of the frame buffer at the core clock rate until the raster sample buffer is full. As the samples are extracted from the raster sample buffer, subsequent image data is pumped into the video encoding system, producing a systolic processing effect.

Abstract: A page based memory address translation table update method and apparatus uses a first processor, such as a host processor or other processor, to notify a second processor to update its own page table. In one embodiment, the first processor generates an execution order driven page table maintenance command for the second processor. The second processor updates its own page table in sequence with received embedded commands. The second processor also updates its own translation look aside buffer in response to the page table maintenance data generated by the first processor. The page table maintenance data may be, for example, a page table maintenance command that is queued by the first processor so that the table update for the second processor is deferred from the first processors point of view since the second processor performs its own page table edits based on the order in which the page table maintenance command appears in a command queue for the second processor.

Abstract: A method and apparatus for detecting an interrupt request in a video graphics or other system are accomplished by reading or polling a shared interrupt request flag stored in one of multiple potentially interrupting devices and determining whether a pending interrupt request exists based on a status of the shared interrupt request flag. In the event that a pending interrupt request exists, a notification of the pending interrupt request is provided to an interrupt service routine. In the event that a pending interrupt request does not exist the circuitry that is reading or polling the shared interrupt request flag delays for a polling interval and then repeats reading or polling the shared interrupt request flag and determining whether a pending interrupt request exists.

Abstract: A method and apparatus for associating memory locations with cache locations includes processing that begins by receiving a request for access to a memory block of memory from one of a plurality of clients. A client may be a host processor, a video graphics processor, or an application running on a host processor or video graphics processor. The processing continues by determining whether a physical cache address associated with the memory block is identified in a flush buffer when the memory block is not currently allocated a logical cache address. The logical cache address is utilized by the system memory controller to allocate a physical cache address of the cache to the memory block. The flush buffer contains addresses of physical cache locations that have been identified to be flushed back to the memory, but are not directly accessible by the host processor since the logical address allocation has been deleted.

Abstract: An amorphous metal alloy strip is disclosed having a width greater than about one inch and a thickness less than about 0.003 inch, this alloy consists essentially of 77 to 80 atomic percent iron, 12 to 16 atomic percent boron and 5 to 10 atomic percent silicon with incidental impurities. The strip has a 60 cycle per second core loss of less than about 0.100 watts per pound at 12.6 kilogauss, saturation magnetization of at least 15 kilogauss, and a coercive force of less than about 0.04 oersteds. Such alloy is further characterized by increased castability and the strip produced therefrom exhibits at least singular ductility. A method of producing such optimum strip is also disclosed.

Abstract: A locking assembly and a process for electrode or ingot formation that include a stub, a locking member, and a support member. The locking member removably extends through the support member and at least a portion of the stub. Molten material is introduced over the support member and the stub to form the electrode. The electrode and integrated stub may be incorporated into an electrode assembly, including a yoke, a fastening member, a shoe, and a conducting tube.

Abstract: A process for producing a steel includes subjecting at least a portion of a melt of the steel to electroslag remelting and, in a subsequent step, heating the steel to a temperature at least as great as the lowest temperature at which all carbides that can form in the remelted steel will dissolve and no greater than the nil ductility temperature of the of the remelted steel, and maintaining the temperature for a period of time sufficient to dissolve primary and clustered carbide particles in the remelted steel greater than 15 micrometers in length. A novel martensitic stainless steel also is disclosed including 0.65 to 0.70 carbon; 0 to 0.025 phosphorus; 0 to 0.020 sulfur; 0.20 to 0.50 silicon; at least one of greater than 0.0004 boron and greater than 0.03 nitrogen; 0.45 to 0.75 manganese; 12.7 to 13.7 chromium; and 0 to 0.50 nickel.

Abstract: A cutting tool or drill insert with chip control geometry comprising a body including a portion securable in a holder and a forward portion. The forward portion defining at least one cutting edge extending from the central axis of the body to an edge of the body. A chip groove is defined by the surface of the body adjacent to the cutting edge. The chip groove incorporates chip control geometry as spaced apart elongate projections.

Abstract: A universal asynchronous receiver transmitter (UART) emulation stage for modem communication uses a digital signal processor containing a software UART control program for sending UART control signals to hardware based UART emulation circuitry. The software UART control program communicates to a modem application interface program that is under control of a host processor. The UART emulation circuitry that is responsive to the control signals from the digital signal processor, includes dedicated transmit and receive FIFO buffer memory for storing modem data and also includes interrupt generation logic to generate an interrupt for the digital signal processor when the received FIFO buffer memory is at a predetermined threshold. The UART emulation circuitry also includes programmable control logic for facilitating host processor interrupt pacing to maintain high compatibility with legacy applications, namely DOS based applications.

Abstract: A method and apparatus for booting up a computing system having enhanced graphics and increased boot up speed begins by obtaining header information from a graphics controller. The header information includes a ROM signature, initialization size of the boot up algorithm, an entry point for the boot up algorithm, and at least one extended mode identifier. The processing then continues by interpreting the header information to determine whether the graphics controller is to boot up in an extended operating mode. When the graphics controller is to boot up in the extended operating mode, the processing continues by allocating memory for storing a boot up algorithm of the graphics controller. Next the processing continues by providing an address pointer to the graphics controller, where the address pointer points to the memory where the boot up algorithm is stored.