Abstract: In a transmitter that includes a plurality of partitioned DAC processing cells coupled to a corresponding plurality of partitioned encoder processing cells, a method for processing signals may include aggregating outputs of each of the plurality of partitioned DAC processing cells to generate an analog output signal. The transmitter may be a direct drive transmitter. The generated analog output signal may be a reduced emissions analog signal. The plurality of encoder processing cells may be partitioned into at least a group of odd encoder processing cells and a group of even encoder processing cells. The plurality of DAC processing cells may be partitioned into at least a group of odd DAC processing cells for processing outputs of the group of odd encoder processing cells and a group of even DAC processing cells for processing outputs of the group of even encoder processing cells.

Abstract: Radio frequency amplifier with constant gain setting. A circuitry that includes triple well connected MOSFETs is employed to eliminate body effects therein. The voltage gain as presented herein, being implemented using a ratio of certain elements within the circuitry, is immune to variations in temperature, power supply voltage, and process variations. One implementation employs an array of selectable MOSFETs to allow for more than one gain setting to be provided by the amplifier. Such an amplifier has a variable/selectable gain setting. An appropriately placed MOSFET is employed to provide the desired input impedance (e.g., 50?). This design can be implemented using multiple n-channel metal oxide semiconductor field-effect transistors (N-MOSFETs) (some of which are triple well connected) and p-channel metal oxide semiconductor field-effect transistors (P-MOSFETs), or alternatively using P-MOSFETs and N-MOSFETs.

Abstract: Performing multiple Reed-Solomon (RS) software error correction coding (ECC) Galois field computations simultaneously in a RISC processor. A means is presented by which multiple Galois field computations are performed in parallel with one another. Processor, memory, and plurality of adders and/or multipliers are implemented appropriately to allow parallel Galois field computations to be performed. Multiplexing can be performed to govern the writing of resultants (generated using the adders and/or multipliers) back to the memory via feedback paths. This approach allows for parallel (as opposed to serial) implementation of the software ECC corrections with minimal area and power impact. In other words, very little space is required to implement this approach is hardware with nominal increase in power consumption, and this slight increase in power consumption provides a significant increase in ECC correction capability using this approach.

Abstract: Current-controlled CMOS (C3MOS) fully differential integrated wideband amplifier/equalizer with adjustable gain and frequency response without additional power or loading. A novel approach is presented by which adjustable amplification and equalizer may be achieved using a C3MOS wideband data stage. This may be referred to as a C3MOS wideband data amplifier/equalizer circuit. This employs a wideband differential transistor pair that is fed using two separate transistor current sources. A switchable RC network is communicatively coupled between the sources of the individual transistors of the wideband differential transistor pair. There are a variety of means by which the switchable RC network may be implemented, including using a plurality of components (e.g., capacitors and resistors connected in parallel).

Abstract: The present invention provides apparatus and methods for performing payload header suppression (PHS), expansion, and verification in hardware. A PHS verify circuit reads a data packet until it reaches the location where the first byte must be compared to PHS rule verify bytes. Next, all the relevant bytes in the payload header are compared to the PHS rule verify bytes obtained from a payload header suppression rule mask. Upon completion of the compare, a flag is generated to a PHS suppress circuit indicating that verification has passed or failed. For payload headers passing the verification process, one or more bits are suppressed in the payload header and a the payload header suppressed and a payload header suppression index is added to the suppressed packet payload header. Following transmission, the suppression indexed is used to identify the bits to be reinserted into the suppressed payload header.

Abstract: An imaging device includes a plurality of photo-diodes that operate as optical pixels arranged in a plurality of columns on a single CMOS substrate. The outputs of the multiple pixel sensors, or photo-diodes, are examined to determine if a one pixel, or a region of pixels are in saturation. If so, then the pixel gain is adjusted to correct or compensate for the image distortion in the region. For example, the gain of the charging amplifier or operational amplifier can be adjusted to correct for saturation. This can be done in real-time since hardware is being tuned for the correction instead of software.

Abstract: In RF transceivers, a method and a system for a frequency feedback adjustment in digital receivers are provided. A DC offset may result from the difference in frequencies between an RF transmitter and an RF receiver. An adjustment of the receiver's frequency may be implemented after synchronization occurs and may be performed by utilizing the Forward Error Correction (FEC) repetition rate in a header of a Bluetooth packet. The adjustment may be performed when the frequency difference exceeds a threshold value. In another aspect, adjusting the frequency of the RF receiver may be performed by modifying and/or changing a phase locked loop (PLL) trimmer register. This approach may allow an RF receiver to operate, in some instances, without the need for an equalizer. In this regard, the power consumed by the RF receiver may be minimized and/or the overall cost of the RF receiver may be reduced.

Abstract: A charge pump circuit that supplies current to an offset current of an output signal for an oscillating circuit is disclosed. The charge pump circuit includes a first switch and a second switch. The first switch is coupled to a gate of an output diode that provides a charge up current from the charge pump circuit. A second switch is coupled to an anode of the output diode and supplies the charge up current to the output diode. The first switch comprises a first state and the second switch comprises a second state that is opposite the first state. Thus, when the second switch is on, the first switch is off. The charge pump circuit also includes a capacitance to hold a bias voltage when the first switch is off.

Abstract: Provided is an architecture for a cryptography accelerator chip that allows significant performance improvements over previous prior art designs. In various embodiments, the architecture enables parallel processing of packets through a plurality of cryptography engines and includes a classification engine configured to efficiently process encryption/decryption of data packets. Cryptography acceleration chips in accordance may be incorporated on network line cards or service modules and used in applications as diverse as connecting a single computer to a WAN, to large corporate networks, to networks servicing wide geographic areas (e.g., cities). The present invention provides improved performance over the prior art designs, with much reduced local memory requirements, in some cases requiring no additional external memory. In some embodiments, the present invention enables sustained full duplex Gigabit rate security processing of IPSec protocol data packets.

Abstract: A method and system for configurable drain for two-way handshake system is provided and may comprise coupling a transmitting device to a drain bucket, and draining unwanted data at the transmitting device. The drain bucket may be configurably coupled to the transmitting device via a switch, where the switch may be a crossbar switch. The drain bucket may receive at least one transmitter handshake signal from at least one transmitting device. The drain bucket may transmit at least one receiver handshake signal to the at least one transmitting device. The receiver handshake signal may be asserted at least as long as the received transmitter handshake signal is asserted. The receiver handshake signal may be based on the received transmitter handshake signal. For example, the received transmitter handshake signal may be looped back by the receiver as the receiver handshake signal.

Abstract: Iterative metric updating when decoding LDPC (Low Density Parity Check) coded signals and LDPC coded modulation signals. A novel approach is presented for updating the bit metrics employed when performing iterative decoding of LDPC coded signals. This bit metric updating is also applicable to decoding of signals that have been generated using combined LDPC coding and modulation encoding to generate LDPC coded modulation signals. In addition, the bit metric updating is also extendible to decoding of LDPC variable code rate and/or variable modulation signals whose code rate and/or modulation may vary as frequently as on a symbol by symbol basis. By ensuring that the bit metrics are updated during the various iterations of the iterative decoding processing, a higher performance can be achieved than when the bit metrics remain as fixed values during the iterative decoding processing.

Abstract: The invention provides a system and method for updating software in the CPU of a network device without interrupting the operation of the network device. The invention determines whether operating state information is recoverable. If it is not recoverable, then it will be stored in a metadata module or reload buffer. When the CPU is rebooted, after a software update or crash, it operates in a special reload mode and is able to recover any system state information not available in the network device from the metadata module.

Abstract: A high-speed, low leakage-power Standard Cell Library is provided. The high-speed, low-leakage-power Standard Cell Library provides the extra drive-strength of a taller X-Track library (e.g., 14-Track library) and low leakage-power comparable to that of a smaller, N-Track library (e.g., 10-Track library). The high-speed, low leakage-power Standard Cell Library includes a set of cells each having a device area designed to provide maximum drive strength for the cell. The high-speed, low leakage-power Standard Cell Library further includes a second set of cells having varying device areas that provide reduced leakage power characteristics comparable to cells in the smaller, N-Track library. The modified reduced leakage-power cells are formed by adding padding to the cell to achieve a desired leakage-power characteristic of the cell.

Abstract: A system and method for substituting data packets into a data stream, is provided. In one embodiment, the data stream is a video data stream. The system includes packet buffers, a multiplexer, a packet substitution controller, a direct memory access (DMA) engine and a link list buffer controller. A method is also provided for substituting data packets - containing information of the same or different type—into a video data stream at variable rates using a selection mechanism driven by link list buffer control.

Abstract: A communication system includes a first device and a second device that can advertise multiple capabilities using communication links. A first type of auto-negotiation between the first and second devices is performed using a first communication link between the devices. A second communication link between the devices is used to facilitate a second type of auto-negotiation. For example, the first communication link can include pairs A and B of an IEEE Std. 802.3 four twisted pair cable. The second communication link can include pairs C and D of the cable.

Abstract: A system, method and apparatus are described herein that allow a mix computers or other devices that are configured for communication in accordance with different network layer protocols, such as Internet Protocol version 4 (IPv4) and Internet Protocol version 6 (IPv6), to share a single physical connection to a WAN. To achieve this, a networking device such as a router resides between a plurality of local devices and the physical connection to the WAN and routes network layer packets between the local devices and the WAN. The networking device determines whether each local device is IPv4-capable or IPv6-capable. Based on this determination, the networking device selectively applies Network Address Translation (NAT) and optional firewall functionality to network traffic originating from or destined for the IPv4-capable devices, while bypassing such functionality for IPv6 network traffic originating from or destined for the IPv6-capable devices.

Abstract: An apparatus for maintaining synchronization with a plurality of asynchronous communication links includes a first counter that generates a first local network clock, and a second counter that generates a second local network clock. The apparatus also includes an offset controller coupled with the first counter and coupled with the second counter, the offset controller configured to load a current network clock value of a first network clock of a first communication link into the first counter, and to load a current network clock value of a second network clock of a second communication link into the second counter. The apparatus further includes a drift controller coupled with the first counter and with the second counter, the drift controller configured to correct a drift between the first local network clock and the first network clock and to correct a drift between the second local network clock and the second network clock.

Abstract: A triggered restart mechanism for failure recovery in power over Ethernet (PoE). Powered devices (PDs) that fail can be remotely recycled by a power sourcing equipment (PSE). After detection of a failure of a PD, such as by the failure to receive a status message, a PSE can generate a reset signal (e.g., power cycle, reset pulse, etc.) on the port. This reset signal can cause the PD to perform a full power cycle or quick restart.

Abstract: Systems and methods are described for performing packet loss concealment using an extrapolation of an excitation waveform in a sub-band predictive speech coder, such as an ITU-T Recommendation G.722 wideband speech coder. The systems and methods are useful for concealing the quality-degrading effects of packet loss in a sub-band predictive coder and address some sub-band architectural issues when applying excitation extrapolation techniques to such sub-band predictive coders.

Abstract: The invention enables a reversing IQ polarity in a bandpass filter so that the bandpass filter can filter signals with high side or low side injection.