Abstract: Aspects of the invention may include a method updating a color look-up table (CLUT) for a next line of graphics before a current line of graphics has been completely read out of a graphics FIFO and assigned color pixel values. The method may include the step of formatting or arranging the CLUT into a plurality of sub-CLUTs. Each one of the sub-CLUTs may include pixel color values for each one of a plurality of pixels which may include a line of the graphics image data. Pixel color values may be read from within a first selected sub-CLUT, the first selected sub-CLUT comprising pixel color values for a first line of the graphics image data. The read pixel color value may be applied to the current first line of the graphics image data. While the read pixel color value is being applied to the current first line, pixel color values for a second selected sub-CLUT may be updated. The second selected sub-CLUT may include color pixel values for a second line of the graphics image data.

Abstract: The present invention is related to a method and apparatus for managing memory in a network switch, wherein the memory includes the steps of providing a memory, wherein the memory includes a plurality of memory locations configured to store data therein and providing a memory address pool having a plurality of available memory addresses arranged therein, wherein each of the plurality of memory addresses corresponds to a specific memory location. The method further includes the steps of providing a memory address pointer, wherein the memory address pointer indicates a next available memory address in the memory address pool, and reading available memory addresses from the memory address pool using a last in first out operation. The method also includes writing released memory addresses into the memory address pool, adjusting a position of the memory address pointer upon a read or a write operation from the memory address pool.

Abstract: A system and method for determining whether to process a signal using three-dimensional comb filtering. Various aspects of the present invention may comprise method steps and system components that generate an inter-frame chroma signal. Various aspects may generate a filtered inter-frame chroma signal by removing a band of frequency components from the inter-frame chroma signal that generally corresponds to chroma signal components. Various aspects may analyze the filtered inter-frame chroma signal to determine whether three-dimensional comb filtering may be appropriate. Various aspects may comprise method steps and components that generate inter-frame and intra-frame luma signals. Various aspects may generate filtered inter-frame and intra-frame luma signals by removing frequency components from the inter-frame and intra-frame luma signals, respectively, that fall outside a frequency band near the chroma sub-carrier frequency.

Abstract: An on-chip baseband-to-RF interface includes a receive/transmit section, a control section, and a clock section. The receive/transmit section, when in a receive mode, provides the stream of inbound symbols from the RF circuit to the baseband processing module and, when in a transmit mode, provides the stream of outbound symbols from the baseband processing module to the RF circuit. The control section provides a control communication path between the baseband processing module and the RF circuit. The clock section provides a clock communication path between the baseband processing module and the RF circuit.

Abstract: A method for receiving data from a plurality of virtual channels begins by storing a stream of data as a plurality of data segments, wherein the stream of data includes multiplexed data fragments from at least one of the plurality of virtual channels, and wherein a data segment of the plurality of data segments corresponds to one of the multiplexed data fragments. The method continues by decoding at least one of the plurality of data segments in accordance with one of a plurality of data transmission protocols to produce at least one decoded data segment. The method continues by storing the at least one decoded data segment, in a generic format, to reassemble at least a portion of a packet provided by the at least one of the plurality of virtual channels. The method continues by routing the at least one decoded data segment as at least part of the reassembled packet to one of a plurality of destinations in accordance with the at least one of the plurality of virtual channels.

Abstract: A method and system for combining requests for data bandwidth by a data source for transmission of data over a wireless communication medium is provided. A central node receives one or more bandwidth requests from one or more data sources via wireless communication. A scheduler then combines one or more bandwidths requests from the same data source to create a single data burst bandwidth. The central node then grants the data burst bandwidth to the appropriate data source via wireless communication.

Abstract: Aspects for measuring receiver mixer IQ mismatch in a transceiver are described. The measuring includes providing a training signal for a receiver mixer, the training signal having periodic, uncorrelated I and Q signals. A phase mismatch in the receiver mixer is determined from IQ correlation over a unit period. A gain mismatch in the receiver mixer is determined from a power estimate of both I and Q signal for the unit period.

Abstract: A low efficiency integrated circuit (IC) antenna includes an antenna element and a transmission line. The antenna element is on a first metal layer of a die and has a length less than approximately one-tenth of a wavelength or greater than one-and-one-half times the wavelength for a frequency band of approximately 55 GHz to 64 GHz. The transmission line is on the die and is electrically coupled to feed points of the antenna element.

Abstract: The invention enables a reversing IQ polarity in a bandpass filter so that the bandpass filter can filter signals with high side or low side injection.

Abstract: A clock circuit includes a waveform generator, a comparison module, and a clock signal module. The waveform generator is coupled to generate a waveform based on a reference oscillation. The comparison module is coupled to compare the waveform with a plurality of references to produce a plurality of waveform comparisons. The clock signal module is coupled to generate a clock signal from the plurality of waveform comparisons.

Abstract: Quadrature receiver sampling architecture. A signal ADC performs analog to digital conversion for both I and Q streams. An analog MUX selects the appropriate I and the Q baseband analog input streams for input to the ADC at the appropriate time. A digital filter may also be employed to compensate for any introduced delay between the samples of the I and Q channel when seeking to recover the symbols that have been transmitted to a communication receiver that employs this quadrature receiver architecture and/or signal processing. In one embodiment, if an ADC is clocked at a rate of substantially twice the sample rate of the I and Q channels, there will be a one-half sample clock delay between the digital I and digital Q data at the output of the ADC. This delay is then removed before the demodulator processes the input signals to recover the transmitted symbols.

Abstract: Certain aspects of a method and system for transparent TCP offload with a user space library are disclosed. Aspects of a method may include collecting TCP segments in a network interface card (NIC) without transferring state information to a host system. When an event occurs that terminates the collection of TCP segments, a single aggregated TCP segment based on the collected TCP segments may be generated. The aggregated TCP segment may be posted directly to a user space library, bypassing kernel processing of the aggregated TCP segment.

Abstract: A balun that includes a first conductor, a second conductor, and a third conductor. The first conductor has a first length. The first conductor also has a first end connected to a first balanced power amplifier output port. The second conductor has substantially the same first length. The second conductor also includes a first end connected to a second balanced power amplifier output port and a second end connected to a second end of the first conductor. The third conductor has substantially the same first length. The third conductor has a first end connected to an antenna port and a second end connected to a ground potential.

Abstract: An Internet infrastructure with network devices and end point devices containing service module manager and service modules supports packet routing and vectoring based on payload comparison with spatially related templates. The network device supports packet content analysis on arriving packet, consists of a plurality of packet switched interface circuitries, user interface circuitry, local storage comprising the service module manager software and a plurality of local service modules, and processing circuitry communicatively coupled to each of the packet switched interfaces, local storage and user interface circuit. The service module manager contains, for comparisons, header templates, spatially related payload trigger templates and spatially related payload supplemental templates. The spatially related templates attempt to identify a target data with certainty. The processing circuitry takes one or more actions on the packet of target data, by applying selected service modules.

Abstract: A system and method for detecting the presence and location of pull-down fields in a video field stream. Various aspects of the present invention may comprise method steps and circuit structure for generating an array of variance indications, each of which represents a degree of variance between two video fields in the video field stream. Various aspects may comprise comparing the array of variance indications to a pattern to detect a pull-down field in the video field stream. Various aspects may comprise comparing corresponding portions of video fields and generating a histogram of differences between the corresponding portions. Various aspects may comprise generating an indication of variance of the histogram and analyzing the indication of variance. Various aspects may comprise analyzing an array of such indications of variance and may comprise comparing the array of such indications to a pattern or plurality of patterns.

Abstract: Methods for assembling a die-down array integrated circuit (IC) device packages with enhanced thermal, electrical, and input/output properties are presented. The method includes coupling a first surface of a substrate to a first surface of a heat spreader, mounting a first surface of an IC die to the first surface of the heat spreader within a central cavity of the substrate, coupling a plurality of bond pads on a second surface of the IC die to corresponding bond pads on a second surface of the substrate with a plurality of wire bonds, and coupling a first surface of an interposer to the second surface of said IC die. A central opening is open at the first surface of the substrate and the second surface of the substrate. The central opening overlaps the central cavity formed in the first surface of the heat spreader. A plurality of electrically conductive bumps on the second surface of the IC die are coupled to corresponding bond pads on the first surface of said interposer.

Abstract: A mixer for a radio transceiver includes a commutating mixer switch having a first differential input port coupled to a DC offset cancellation path. The first differential input port of the mixer switch includes a first terminal coupled to a first end of a first resistor and a second terminal coupled to a first end of a second resistor. Second ends of the first and second resistors are configured to receive a differential input signal. The DC offset cancellation path may provide a resistively coupled DC calibration signal for reducing the magnitude of DC offsets that may be present at the input of the mixer switch. The concept can be used for either image or non-image reject mixers.

Abstract: A request from a first processor for access to a shared resource in a computing system is received, and access is provided to the shared resource by the first processor at a first clock frequency. A request from a second processor for access to a shared resource in a computing system is received, and access is provided to the shared resource by the second processor at a second clock frequency that is lower than the first clock frequency.

Abstract: A disclosed exemplary embodiment is a phase locked loop comprising a main charge pump driven by a phase error signal, and providing a first input to a loop filter. An auxiliary charge pump driven by the phase error signal feeds a second input of the loop filter. The loop filter can be an active loop filter comprising an operational amplifier and a feedback RC network. The first input of the active loop filter can be an inverting input of the operational amplifier and the second input can be a non-inverting input of the operational amplifier. An on-chip stabilizing capacitor fed by the auxiliary charge pump and coupled to the second input of the loop filter is significantly smaller than the conventional stabilizing capacitors. The loop filter outputs a regulating voltage for regulating the oscillation frequency of a voltage controlled oscillator in the phase locked loop.

Abstract: Digitally controlled phase interpolator circuit. A phase selection control word undergoes decoding to generate a switch control word. The phase selection control word includes 2 quadrant indicating bits and phase interpolating bits for a 4 clock scheme (e.g., 4 clocks having phases 0°, 90°, 180°, and 270°). Such a phase selection control word could includes 3 sector indicating bits and phase interpolating bits for an 8 clock scheme (e.g., 8 clocks having phases 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°). The gates of a number of differential pairs of transistors receive the various clock signals. A number of switching circuits direct current from corresponding current sources/supplies to coupled sources of the differential pairs of transistors, and an output clock is taken from coupled drains of the differential pairs of transistors. One or more current sources/supplies can be implemented to provide continuous current (e.g., in an always on manner) to the differential pairs of transistors.