Abstract: Formal techniques are applied to industrial design problems such as verification of a circuit design. Initial decisions may include defining properties to verify the design. An abstraction of the design may be generated and model checking applied to the abstraction. Results obtained using these techniques may be extended by performance analysis and/or verification of sequential operations.

Abstract: A system and method providing output voltage control in a power supply circuit. Various aspects of the present invention may comprise at least a first module adapted to receive an input DC voltage and at least one voltage control signal and output an output DC voltage that is a function of the input DC voltage and the voltage control signal. At least a second module may be adapted to receive a feedback signal representative of the output DC voltage and output the at least one voltage control signal as a function of at least the feedback signal. The second module may, for example, be a digital module adapted to generate the at least one voltage control signal utilizing digital active components. The second module may also, for example, utilize transistors and/or passive components controlled by the digital active components to generate the at least one voltage control signal.

Abstract: An integrated multimode radio includes a multimode receiver and a multimode transmitter. The multimode receiver includes a shared receiver front-end, a receiver multiplexor, and a plurality of receiver IF stages. The multimode transmitter includes a shared transmitter front-end, a transmitter multiplexor, and a plurality of transmitter IF stages.

Abstract: A fine granularity, wide-range variable gain amplifier (“VGA”) comprises an attenuator, a high gain signal path, a low gain signal path and a gain adjustment control to adjust a gain of the VGA, wherein the gain adjustment control is configured to cause a selective activation of at least a portion of the low gain signal path or the high gain signal path to achieve a desired overall gain.

Abstract: A system and method for substituting data packets into a data stream, is provided. In one embodiment, the data stream is a video data stream. The system includes packet buffers, a multiplexer, a packet substitution controller, a direct memory access (DMA) engine and a link list buffer controller. A method is also provided for substituting data packets—containing information of the same or different type—into a video data stream at variable rates using a selection mechanism driven by link list buffer control.

Abstract: A method of communicating data to M receiving antennas from N transmitting antennas, where M and N are integers, the method includes the steps of receiving M data signals from M receive antennas, applying the M data signals to a space/time decoder to produce M decoded streams and reconstructing original data transmitted via N transmit antennas from the M decoded streams. At least P transmitting antennas transmit space-time block-coded signals and (N-P) transmitting antennas transmit code signals through spatial division multiplexing, where P is an integer.

Abstract: A method and system that configure communication between devices in a network utilizing bluetooth technology, where one device may or may not support content protection, and another device may or may not support content protection. A first device may utilize a configuration that enables data communication via a bluetooth communication link with a second device based on whether the second device supports content protection. The content protected data communicated between the devices is based on the first device configuration. If the second device does not support content protection, the first device may utilize a configuration that does not require content protection for communicating data with the second device. If the second device supports content protection, the first device may utilize a configuration that requires content protection for communicating data.

Abstract: A programmable transmitter generates a frame preamble to train a receiver with respect to a communication link format that corresponds to a transmission mode wherein the transmission mode may comprise transmitting the communication link over one or more antennas. Generally, the invention includes generating a preamble with an arrangement that depends upon whether a Greenfield (high data rate) or mixed mode transmission is to occur and that depends upon a number of spatial streams that are to be generated. One format for high data rate transmission includes a short training sequence, a long training sequence and a signal field. The mixed mode transmission further includes a legacy prefix.

Abstract: A radio transceiver device includes circuitry for radiating electromagnetic signals at a very high radio frequency both through space, as well as through wave guides that are formed within a substrate material. In one embodiment, the substrate comprises a dielectric substrate formed within a board, for example, a printed circuit board. In another embodiment of the invention, the wave guide is formed within a die of an integrated circuit radio transceiver. A plurality of transceivers with different functionality is defined. Substrate transceivers are operable to transmit through the wave guides, while local transceivers are operable to produce very short range wireless transmissions through space. A third and final transceiver is a typical wireless transceiver for communication with remote (non-local to the device) transceivers.

Abstract: Aspects of the method and system for rejecting single sided leakage into an amplitude modulated channel may comprise an AM demodulator for demodulating a received composite broadcast signal's control channel to generate an amplitude modulated (AM) component. A PM demodulator may demodulate a received composite broadcast signal's control channel to generate a phase modulated (PM) component. At least one subtractor may subtract an AM leakage component and a PM leakage component contributed by the single sided leakage in the received composite broadcast signal's control channel. The system may comprise at least one of each of AM and PM bandpass filters and envelope detectors that filter and detect envelopes of the AM and PM components at 982.5 Hz and 922.5 Hz.

Abstract: Sample rate reduction in data communication receivers. Digital sampling of analog data is performed using a reduced sample rate. The reduction factor may be any number of factors including a factor that divides the sample rate by a factor of two. The reduction of the sampling frequency is from a sampling frequency that is greater than twice the highest frequency component in an analog input signal. These analog input signals may be I and Q streams in certain embodiments. A digital interpolation filter may be employed to increase (up-convert) the sample rate of a digital signal before it is input to a VID filter that is used to recover the transmitted symbols from the over-sampled data stream. In this embodiment, this technique allows a front end of a communication receiver to be clocked at a lower sampling rate without affecting the performance of the VID filter.

Abstract: A communication system includes a first device and a second device that can advertise multiple capabilities using communication links. A first type of auto-negotiation between the first and second devices is performed using a first communication link between the devices. A second communication link between the devices is used to facilitate a second type of auto-negotiation. For example, the first communication link can include pairs A and B of an IEEE Std. 802.3 four twisted pair cable. The second communication link can include pairs C and D of the cable.

Abstract: Aspects of the present invention may be found in a system and method to more effectively detect and correct irregularities of video in a pull-down video signal, such as a 3:2 (or 2:2) pull-down video signal. Various aspects of the present invention provide a system and method to determine when the cadence of pull-down video has changed. This may occur, for example, when a bad-edit is encountered in the pull-down video. Other aspects of the present invention may be found in a system and method of detecting and correcting distortion or artifacts occurring at the pixel level. The distortion or artifacts are detected and corrected at a per-pixel level while performing a reverse pull-down of the video signal. Finally, aspects of the invention allow the automatic enabling of per-pixel correction when performing a reverse 3:2 directed weave. A computed variable is used to automatically activate the per-pixel correction.

Abstract: The present invention provides a modular wireless headset with which to service multiple incoming audio streams. This modular wireless headset includes a wireless microphone and wireless earpiece. The wireless earpiece may exchange radio frequency (RF) signals with a base unit and render content contained within the exchanged RF signals to a user. This wireless earpiece further includes a wireless interface, a processor, a speaker, a user interface, and an authentication module. The wireless interface allows the earpiece to wirelessly communicate with the base unit. The processor recovers communications exchanged with the base unit that the speaker then renders audible. A user interface coupled to the processor may alert the user to any additional incoming audio communications. Having received the alert, the user may select between the communications.

Abstract: A method and system are disclosed for testing for double shift errors in at least one scan chain of flip-flops during a simulation of the design of a digital integrated circuit chip. At the start of the simulation, outputs of each flip-flop in the scan chain are initialized to a same known symbol (e.g., ‘X’). The flip-flops in the scan chain are clocked to shift binary digital symbols (zeros and ones) into the first flip-flop and through the successive flip-flops in the scan chain. During the shifting and clocking process, successive, contiguous pairs of flip-flop outputs are compared, one pair after each clock cycle. A double shift error is declared between the first flip-flop in the pair and the second flip-flop in the pair if the output symbols of the pair are the same.

Abstract: In a video system, a method and system for design verification of video processing systems with unbalanced data flow are provided. Efficient design verification may be provided for multi-field video processors with separate control data flow and video data flow. A design verification architecture may utilize a reference model to generate test and expected data for a controller and/or a data processor in a multi-field video processor hardware model. The design verification architecture may provide test data via stimulus feeders and may compare simulated and expected data in result checkers. When the controller is selected for verification, the design verification architecture may verify the operation and design of the multi-field video processor control data flow implementation. When the data processor is selected for verification, the design verification architecture may verify the operation and design of the multi-field video processor video data flow implementation.

Abstract: A charge pump includes a resistor divider connected between an output voltage node and ground and a comparator inputting a reference voltage at one input, and a divided voltage from the resistor divider at another input. A digital control circuit is enabled by the comparator. A first transistor and a second transistor are in series between an input voltage node and the ground, both transistors controlled by the digital control circuit. A pump capacitor is connected between to the output voltage node and between the first and second transistor, and being charged by turning the first and second transistors on and off. A first diode is between the pump capacitor and the input voltage node. A second diode between the pump capacitor and the output voltage node. A reservoir capacitor between the output voltage node and ground. The digital control circuit comprises a first shift register.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: Certain embodiments of the invention may be found in a method and system for antenna selection diversity with prediction. An antenna diversity system may use information that it has stored on the antenna selection process in previous frames to predict the starting receiving antenna and the starting transmission antenna for the next frame. The prediction may be based on which antennas were selected in previous frames or may be based metrics associated with performance of the antennas. Prediction may be based on a majority polling scheme of previously selected antennas in a determined number of previous frames. Prediction may also be based on a weighted sum of at least one selection metric for all antennas in a determined number of previous frames. Antenna prediction provides a significant performance improvement by reducing the processing and operational overhead in cases where a transmit or a receive antenna dominates.

Abstract: A short length LDPC (Low Density Parity Check) code and modulation adapted for high speed Ethernet applications. In some instances, the short length LDPC code and modulation may be employed within the recommended practices currently being developed by the IEEE 802.3an (10GBASE-T) Task Force. The IEEE 802.3an (10GBASE-T) Task Force has been commissioned to develop and standardize communications protocol adapted particularly for Ethernet operation over 4 wire twisted pair cables. A new LDPC code, some possible embodiments of constellations and the corresponding mappings, as well as possible embodiments of various parity check matrices, H, of the LDPC code are presented herein to provide for better overall performance than other proposed LDPC codes existent in the art of high speed Ethernet applications. Moreover, this proposed LDPC code may be decoded using a communication device having much less complexity than required to decode other proposed LDPC codes existent in this technology space.